Chapter 3: Hardware Design; Hardware Overview - Zynq UltraScale+ User Manual

Hardware Design

Hardware Overview

The Vivado IP integrator flow is used to create the hardware design which is partitioned
between the processing system (PS), RF Data Converter (RFDC), and programmable logic
(PL). Figure 3-1
X-Ref Target - Figure 3-1
DDR
Controller
S_AXI_HP0_FPD
AXI Interconnect
DMA
Channel Select Mux
Stream Pipe
ADC0
RFSoC Data Converter Evaluation Tool User Guide
UG1287 (v2018.2) October 1, 2018
shows the hardware block diagram.
Processing System
GEM
AXI Interconnect
Stream Pipe Stream Pipe
DAC0
ADC7
RFdc
Figure 3-1: Hardware Block Diagram
www.xilinx.com
APU
APU
APU
APU SD
S_AXI_HP1_FPD
AXI Interconnect
DMA
Stream Mux
Stream Pipe
DAC7
Chapter 3
I2C
M_AXI_HPM0_FPD
AXI Smartconnect
DDR4 Controller (MIG)
Clocking and Control
Programmable Logic
X21233-092118
Send Feedback
14