Zynq UltraScale+ User Manual page 16

X-Ref Target - Figure 3-2
AXI
PL DDR + MIG
512 bits x 300 MHz
Figure 3-2: Datapath Implementation for 8-Channel RF-DAC
Figure 3-2 represents the architecture of the 8-channel RF-DAC (RF-DAC0 to RF-DAC7). The
Scatter Gather (SG) DMA is used to source the data from the PL DDR memory controller to
the DACs. The DMA sends this data to the stream MUX block, which is connected to each of
the DAC channel's stream data path. Based on the channel select line input (PS-GPIOs
routed through extended multiplexed I/Os (EMIOs)) of the stream pipe, the data gets
routed to the corresponding RF-DAC channel. (See
replay from DDR, DMA constantly fetches the data and streaming mux switches the channel
based on the user selection of enabled channels. For sample storag e and replay from BRAM
mode, the functionality of the memory loopback system is elaborated upon in
Loopback Details.
RFSoC Data Converter Evaluation Tool User Guide
UG1287 (v2018.2) October 1, 2018
SG DMA Stream Mux
AXI Streaming Interface
256 bits x 300 MHz
www.xilinx.com
Chapter 3: Hardware Design
Memory
Loopback 0
Memory
Loopback 1
Memory
Loopback 2
Memory
Loopback 3
Memory
Loopback 4
Memory
Loopback 5
Memory
Loopback 6
Memory
Loopback 7
256 bits x DAC CLK
GPIO Selection.) In case of continuous
Send Feedback
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
X21293-092118
Memory
16