Spi Connection; Timing Chart - Heartland DT10 Hardware Manual

2.6. SPI connection

2.6.1. Timing chart

SPI bus timing
No.
1 CS (Low) - CLK timing
2 CLK period
3 CLK low period (setup time)
4 CLK high period (hold time)
5 CLK - CS (high) timing
6 CS (high) period
Data is transferred as 1bit parallel and output as MSB First in order of the following items:
・
Latch timing is the rising edge of CLK.
・
1. Argument of _TP_BusOut () dat (16bit)
2. Argument of _TP_BusOut () addr (0 - 24bit)
* The number of "addr" bit varies (0/4/8/12/16/20/24) and high-order bits less than 24bit are treated
as "0".
CS must be set "high", except when outputting the Test Point.
Never set it to "low" when the Test Point output stops.
Caution
Copyright © 2012-2014 Heartland. Data Inc.
Description
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DT10 Hardware Manual
MIN. MAX. UNIT
20 ns
40 ns
20 ns
20 ns
20 ns
20 ns