Gpio Connection 4Bit / 2Bit; Timing Chart - Heartland DT10 Hardware Manual

2.5. GPIO connection 4bit / 2bit

2.5.1. Timing chart

GPIO bus timing
* In the case of "GPIO 2bit", DAT[0:1]
No.
1 CS (Low) - CLK timing
2 Data hold timing
3 Data setup timing
4 CLK switch period
5 CLK - CS (High) timing
6 CS (High) period
Data is transferred as 4bit parallel and output as MSB First in order of the following items:
・
Latch timing is the edge of CLK rising and falling.
・
1. Argument of _TP_BusOut () dat (16bit)
2. Argument of _TP_BusOut () addr (0 - 24bit)
* In the case of 4bit, the number of "addr" bit varies (0/4/8/12/16/20/24) and high-order bits less
than 24bit are treated as "0".
* In the case of 2bit, the number of "addr" bit varies (0/2/4/6/8/10/12/14/16/18/20/22/24) and
high-order bits less than 24bit are treated as "0".
CS must be set "high", except when outputting the Test Point.
Never set it to "low" when the Test Point output stops.
Caution
Copyright © 2012-2014 Heartland. Data Inc.
Description
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DT10 Hardware Manual
MIN. MAX. UNIT
20 ns
20 ns
20 ns
40 ns
20 ns
20 ns