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8.1.4
Diagram B04A, Type SVP WX69 (IC7C01), Trident Video processor
Block Diagram
NTSC/PAL/
SECAM
CVBS1
3D Comb
Decoder/
CVBS1
Motion
S-Video
Adaptive De-
interlacing
YPbPr
SXGA RGB
(1280x1024/
Auto Mode/Auto
60)
Tune/Auto
Hsync/
Phase
Vsync
30-bit
Digital
RGB
HDMI
Differential
Signals
I2C
8 bit Add/Data
Pin Configuration
ICSC
BMNR
NR
ME/MC
Frame
Buffer
Controller
Frame
ICSC
Rate
Converter
HDMI
HDCP
CPU &
OSD
Interface
Figure 8-4 Internal block diagram and pin configuration
IC Data Sheets
Luma
Deinterlacer
Cubic4
3:2/2:2 pull
Scalar
down
chroma
Auto Color
Adjustment
Cubic4
ICSC
Deinterlace
scalar
Blender
Chroma Key
VM Control
H&V Voltage
Protection
VBI/OSD/
TELETEXT
Display
I2S SPDIF
LC8.2HA LA
8.
Gamma LUT
Dual
10 bit
LVDS
CRTC/DPLL
Clock PLL
EN 33
LVDS
H Sync
V Sync
Crystal
I_17760_036.eps
260208
2009-Apr-10
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