Vcore Vdd Core - Clevo M740J Service Manual

Schematic Diagrams

VCORE VDD CORE

3 0
3 2
5 , 34 C P U _P W R G D _ S V I D _ R E G
Sheet 33 of 47
VCORE VDD CORE
B - 34 VCORE VDD CORE
P R 14 7 10 K _ 0 4 E N _ V C O R E
5V E N _ V C OR E 3 4
P R 14 6
P R 1 5 0 0 _ 04
V C O R E _ O N
1 00 K _ 0 4
P Q 28
Z 3 3 01 G
2 N 7 0 02 W
P J 9
P R 1 4 8 P Q 27
G 2 N 7 0 0 2W 3m m
C P U _ V D D _ E N
*1 M_ 1 % _ 04
P C 1 8 7
. 1 U _5 0 V _ 0 6
VERY IMPORTANT
PWR_O K sig nal s houkd not be
accid ental ly de -asse rted due t o no ise
or in duced glit ches. To a void any
paras itic de-as serti on, t he us e of an
RC fi lter is ma ndato ry
C P U _ P W R GD _ S V I D _ R E G
P C 2 61 *. 1 U _ X 7 R _ 1 0 V _ 06
E N _ V C OR E P R 2 0 8 0 _ 0 6
Z 3 3 0 2
P R 4 8
P C 6 1
22 _ 0 6
V D D A
P C 5 9 P U 6
2 5
C O MP V 1
2 6
V D D A
2 7
V R E F
2 8
TS E T
2 9
I L I M
3 0
S V D
3 1
S V C
3 2
C O MP V 2
P R 4 6 P R 45
2 . 49 K _ 1 % _ 06 43 . 2 K _ 1 % _0 6
P R 5 2
3 . 3 V S
P C 4 9
5 1 K _ 1 % _ 06
P J8
C P U _ S V D
5, 3 4 C P U _ S V D
3m m
C P U _ S V C
5, 3 4 C P U _ S V C
V F I X _ OZ 8 3 8
P W R GD _ V C O R E P R 4 1
3 2, 3 4 P W R G D _ V C OR E
* 0_ 0 4 0 2_ 5 m i l _ s h or t
P R 3 9
P R 1 4 3 V I N
10 K _ 0 6
27 . 4 K _ 1 % _ 06 P C 4 8
1 0 0 0 P _ 50 V _ 0 6
output volta ge offset
setting resi stors
Single point ground conn ection
P R 1 5 4
R S N 1 V R E F
34 . 8 K _ 1 % _0 6 P R 1 5 5
* 0 _0 6 0 3 _3 2 m i l _ s h or t
6-13-34821-28B
P R 1 4 1
R S N 2
Sig nal Ground Power G round
34 . 8 K _ 1 % _0 6
P R 1 5 2 3 48 _ 0 6
R S P 1 C P U _V D D 0_ R U N _ F B _ H
C P U _ V D D 0 _ R U N _ F B _H
P C 1 8 5
2 2 0 P _ 50 V _ 0 4
R S N 1 C P U _V D D 0_ R U N _ F B _ L
C P U _ V D D 0 _ R U N _ F B _L 5
P R 1 5 3 3 48 _ 0 6
P R 5 1
C S P 1 Z 3 3 07
P C 6 0 1 0 K _ 1% _ 0 6
P R 1 51 P C 1 8 6 P R 1 4 9
10 0 P _ 5 0 V _ 04
5 . 6 K _ 1 %_ 0 6 0 . 1 U _5 0 V _ 0 6 2 . 2 _ 1 % _0 6
3. 3V S
C S N 1
P R 4 7 P C 5 8
* 1 00 K _ 0 4 6 8 0 0 P F _ 5 0V _0 6
P R 49
2 00 _ 0 6 P C 5 7
V I N
5 V
P C 1 7 5 P C 1 7 6
P Q 2 4
I R F 7 41 3 Z P B F < V A L U E > < V A L U E >
H D R 1
L X 1
P C 18 3
. 2 2 U _ 1 6 V _0 6
P Q 26
P D 1 5 A O4 4 56
C A
P R 14 4 P Q 2 5
1 6 2 . 2 _ 1 % _0 6 F M 05 4 0 -N A O 4 4 56
LX 1
1 5 Z 3 3 0 8
B S T 1
1 4 LD R 1
L D R 1
1 3
G N D P
O Z 8 3 8 1 2
V D D P
1 1
L D R 2
1 0 Z 3 3 0 9 P C 1 8 2
B S T 2
9
LX 2
1U _ 10 V _ 0 6
P C 1 7 2 P C 1 7 1
P D 1 4 P Q 2 2
B S T 2 C A I R F 7 41 3 Z P B F < V A L U E > < V A L U E >
F M 05 4 0 -N
P C 1 8 0
. 2 2U _ 1 6V _ 0 6
H D R 2
L X 2
3 . 3 V S
P Q 23 P Q 21
A O 4 4 56 A O4 4 56
P R 4 2
L D R 2
1. 9 1 K _ 0 6
P R 4 0 P R 1 38
Z 3 3 10
5 . 6 K _ 1% _ 0 6 1 0 K _ 1% _ 0 6
P C 1 7 9 P R 1 3 7
C S P 2
P C 5 0 . 1U _ 5 0V _ 0 6 2 . 2 _ 1 % _0 6
1 00 P _ 5 0 V _ 04
C S N 2
P C 5 1
6 80 0 P _ 5 0V _0 6
P R 1 3 9
R S P 2 C P U _ V D D 1 _ R U N _ F B _ H
P C 1 81 34 8 _ 0 6
2 2 0 P _ 5 0V _0 4
P R 1 4 0
R S N 2 C P U _ V D D 1 _ R U N _ F B _ L
C P U _ V D D 1 _ R U N _ F B _L 5
34 8 _ 0 6
5
V I N
P C 4 0
+
1 5 U _ 2 5 V _ D 2
P T H 3
C P U _V D D 0
2 1
18 A
1 00 K _ 0 6
C P U _ V D D 0
P C 17 7 P C 4 2
P R 1 4 5 P L 8 . 5 6U _ 10 * 10 * 4. 1 + +
1 0 _ 0 8
P D 8 33 0 U F _2 . 5 V _ D 3 3 3 0U F _ 2 . 5 V _ D 3
F M 5 82 2 Z 3 3 1 1
P C 1 8 4
1 0 0 0P _5 0 V _ 0 6
Rth1 a nd Rth2 must be placed as close as
possib le to L1 respect ively L2, prefer ably
CLO SE TO P D4
on the same side of th e PCB. Sensing l ines
toward s the controller can be routed o n
P C 44
+ P C 2 6 0
intern al layers to pro vide shielding f rom
1 5 U _ 2 5V _D 2 C A R 4 00 L 1 6 M the in ductors' noise
C P U _V D D 1
18 A
P L7 . 5 6 U _ 1 0 *1 0 *4 . 1
C P U _ V D D 1
P C 16 6 P C 1 5 7
P R 1 36 + +
P T H 2
1 0_ 0 8
P D 7 2 1
F M 5 82 2 3 3 0U F _ 2 . 5V _D 3 3 3 0 U F _ 2 . 5 V _ D 3
1 0 0 K _ 06
Z 3 31 2
P C 1 6 9
1 00 0 P _ 5 0V _0 6
EMI
CP U_ V D D1
C LO SE TO P D7
P C 3 1 * . 0 1U _ 5 0V _0 4
P C 1 6 2 * . 0 1U _ 5 0V _0 4
C P U _ V D D 1 _R U N _ F B _ H 5
P C 4 1
+
* 47 0 U _2 . 5 V _ D
P C 3 9
+
* 47 0 U _2 . 5 V _ D