I/O Ports And Registers; Table 5.1. Function Selection Through Internal Registers - Contec COM-2(PCI) User Manual

I/O Ports and Registers

The board uses a 16552 equivalent as the asynchronous
communication element (ACE) (the COM-8(PCI) uses a 16654
equivalent). For details, refer to the data sheet supplied by Texas
Instruments or other manufacturer. The functions of the eight
consecutive ports from the set I/O address are the same for each
channel. However, on the COM-4(PCI), "top I/O address + 1FH"
for channel 4 is used as the interrupt vector register and therefore
cannot be used as a scratch pad register. On the COM-8(PCI),
"top I/O address + 1FH" for channel 4 and "top I/O address + 3FH"
for channel 8 are used as interrupt vector registers and therefore
cannot be used as scratch pad registers. Table 5.1 lists the
functions of each I/O port.
- COM-2(PCI) has CH1 and CH2 only.
COM-4(PCI) has CH1 to CH4 only.

Table 5.1. Function Selection Through Internal Registers

I/O port address (Starting I/O addresses +xxH)
CH1 CH2 CH3
+0H +8H +10H +18H
+0H +8H +10H +18H
+1H +9H +11H +19H
+2H +AH +12H +1AH +22H +2AH +32H +3AH
+2H +AH +12H +1AH +22H +2AH +32H +3AH
+3H +BH +13H +1BH +23H +2BH +33H +3BH
+4H +CH +14H +1CH +24H +2CH +34H +3CH
+5H +DH +15H +1DH +25H +2DH +35H +3DH
+6H +EH +16H +1EH +26H +2EH +36H +3EH
+7H +FH +17H
+0H +8H +10H +18H
+1H +9H +11H +19H
R : Read only
W : Write only.
DLAB : Divisor Latch Access Bit in the Modem Status Register.
If the high-order DLAB in the line control register is set to 0,
"starting I/O address + 0H" and "starting I/O address + 1H" serve as
the transmission/reception buffer and interrupt mask register,
respectively. If DLAB is set to "1", they serve as frequency-
division registers.
CH4 CH5 CH6 CH7
+20H +28H +30H +38H
+20H +28H +30H +38H
+21H +29H +31H +39H
----- +27H +2FH +37H
+20H +28H +30H +38H
+21H +29H +31H +39H
COM-2(PCI), COM-4(PCI), COM-8(PCI)
DLAB ACE Register (TL16552)
CH8
Receiver (Buffer register)
0
Transmitter (Holding register)
0
Interrupt Enable Register
0
Interrupt ID
×
FIFO Control
×
Line Control
×
Modem Control
×
Line Status
×
Modem Status
×
Scratchpad Register
----- ×
Baud Rate Divider Register LSB
1
Baud Rate Divider Register MSB
1
I/O Ports and Registers
R / W
R
W
R
W
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