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SH7145F
Asynchronous Serial Data Transmission/Reception
On-Chip Peripheral Clock P
This is the reference clock for operation of on-chip peripheral functions. The clock signal is
generated by a clock oscillator.
Receive Shift Register (RSR_1)
This register is used to receive serial data. Serial data is input to RSR_1 from the RxD_1 pin.
When one frame of data has been received, it is automatically transferred to the receive data
register (RDR_1). RSR_1 cannot be accessed by the CPU.
Receive Data Register (RDR_1)
Received data is stored in this 8-bit register. When one frame of data has been received, it is
automatically transferred from RSR_1. RSR_1 and RDR_1 are in a double-buffer
configuration, allowing continuous reception of data. RDR_1 is a receive-only register, so it
can only be read by the CPU.
Transmit Shift Register (TSR_1)
This register is used to transmit serial data. In order to transmit data, the data is first
transferred from the transmit data register (TDR_1) to TSR_1. Then the transmit data is
output from the TxD_1 pin. TSR_1 cannot be accessed directly by the CPU.
Transmit Data Register (TDR_1)
Data to be transmitted is stored in this 8-bit register. When it is detected that TDR_1 is empty,
data that has been written to TDR_1 is automatically transferred to TSR_1. TDR_1 and
TSR_1 are in a double-buffer configuration. This allows data to be transferred to TSR_1 after
one frame of data has been transmitted and the next frame of data is still being written to
TDR_1, making possible continuous transmission of data. It is always possible to read or
write to the TDR from the CPU, but before writing to the TDR it should be confirmed that the
value of the TDRE bit in the serial status register (SSR_1) is 1.
Serial Mode Register (SMR_1)
This 8-bit register is used to select the serial data communication format and the clock source
for the on-chip baud rate generator.
Serial Control Register (SCR_1)
This register is used for transmit and receive control, interrupt control, and to select the
transmit and receive clock source.
Serial Status Register (SSR_1)
This register comprises the SCI1 status flag and the transmit and receive multiprocessor bits.
TDRE, RDRF, ORER, PER, and FER can be cleared only.
Serial Direction Control Register (SDCR_1)
This register is used to select whether the LSB or MSB is first. For 8-bit communication
either LSB-first or MSB-first may be selected, but LSB-first should be used for 7-bit
communication.
REJ06B0357-0100O/Rev.1.00
March 2004
Page 4 of 17
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