Silicon Laboratories C8051F930 User Manual page 7

Table 2. 40-Pin Testcard Connector (J5)
Pin # Description
1 J6/1 (SPI_MOSI)
2 J7/1
3 J6/2 (SPI_SCK)
4 J7/2
5 J6/3 (RF_NSEL)
6 J7/3
7 J6/4
8 J7/4
9 J6/5
10 J7/5
11 J6/6
12 J7/6 (RF_NIRQ)
13 J6/7 (PWRDN)
14 J7/7(RF_NIRQ)
15 J6/8 (GPIO)
16 J7/8(SPI_MISO
17 VDD (3.3 V)
18 VDD (3.3 V)
19 VDD (3.3 V)
20 VDD (3.3 V)
Pin # Description
21 GND
22 J15/1
23 GND
24 J15/2
25 J8/1
26 EBID port (SPI_MOSI)
27 GND
28 EBID port (SPI_MISO)
29 J8/2
30 EBID port (SPI_SCK)
31 GND
32 EBID port (EE_NSEL)
33 J8/3
34 J15/3
35 GND
36 J15/4
37 J8/4
38 J15/5
39 GND
40 J15/6
Rev. 0.3
SDBC-DK3 UG
7