UG-976
EVAL-AD5325DBZ
DAUGHTER BOARD
VREF1
1
5
REFIN
VDD
8
SDA
SDA
U1
AD5325BRMZ
9
SCL
SCL
LK1
VDD
10
A0
GND
7
VDD
+ C6
C5
10µF
0.1µF
C1
DNP
2
VOUTA
C2
3
DNP
VOUTB
4
VOUTC
6
VOUTD
C3
DNP
C4
DNP
Figure 14. Daughter Board Schematics
Figure 15. Daughter Board Component Placement
Figure 16. Daughter Board Top Side Routing
VOUT_A
VOUT_0
DNP
R1
VOUT_B
AGND
VOUT_1
DB6
DB7
DNP
R2
DB8
DB9
DB10
VOUT_C
DB11
CS
VOUT_2
DNP
R3
VOUT_D
VOUT_3
DNP
R4
Rev. A | Page 10 of 13
EVAL-AD5325DBZ User Guide
J2
1
2
SDIN
LDAC
3
4
SDO
CLR
5
6
SCLK
PD
7
8
SYNC
GAIN
9
10
SCL
SDA
J1
1
2
DB0
3
4
DB1
5
6
DB2
7
8
DB3
9
10
DB4
11
12
DB5
13
14
WR
15
16
DGND
J4-1
VOUT_0
J4-2
VOUT_1
J4-3
VOUT_2
J4-4
VOUT_3
J4-5
VOUT_4
J4-6
VOUT_5
J4-7
VOUT_6
J4-8
VOUT_7
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