Table 10: Pin Definition Of The Debug Uart Interface - Quectel UC20 Manual

DTR 66
TXD 67
RXD 68

Table 10: Pin Definition of the Debug UART Interface

Pin Name Pin No.
DBG_TXD 12
DBG_RXD 11
The logic levels are described in the following table.
Table 11: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
UC20 provides 1.8V UART interface. A level translator should be used if your application is equipped with
a 3.3V UART interface. A level translator TXB0108PWR provided by Texas Instruments is
recommended. The following figure shows the reference design of the TXB0108PWR.
UC20_Hardware_Design
DI Data terminal ready.
DO Transmit data.
DI Receive data.
I/O Description
DO Transmit data.
DI Receive data.
Min
-0.3
1.2
0
1.35
Confidential / Released
UMTS/HSPA Module Series
UC20 Hardware Design
1.8V power domain.
1.8V power domain.
1.8V power domain.
Comment
1.8V power domain.
1.8V power domain.
Max
0.6
2.0
0.45
1.8
Unit
V
V
V
V
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