Figure 12: Reference Circuit Of Reset_N By Using Driving Circuit - Quectel UC20 Manual

≥ 150ms
Reset pulse

Figure 12: Reference Circuit of RESET_N by Using Driving Circuit

Figure 13: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated as the following figure.
VBAT
RESET_N
Module
Status
UC20_Hardware_Design
4.7K
S2
TVS
Close to S2
150ms
V ≤ 0.5V
IL
RUNNING
Figure 14: Timing of Resetting Module
Confidential / Released
UMTS/HSPA Module Series
RESET_N
47K
RESET_N
≥ 5s
V ≥ 1.3V
IH
RESETTING
RUNNING
UC20 Hardware Design
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