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Ca r r i e r Board
the ISA bus cycle.
RSTDRV (RES-DRV)
This signal is asserted during POWER-ON period and reset
period. It is used to reset ISA device.
REFSH# (REFRESH#)
This signal is used for I/O device to recharge on-board
DRAM.
SYSCLK
ISA Bus clock signal. It provide I/O device internal state
machine clock source.
OSC (SIOCLK)
14.31818MHz clock source.
IRQ3 – IRQ15 (Not include IRQ8, IRQ12, IRQ13)
Interrupt request signals.
MASTER#
This signal indicates a 16-bit ISA master is taking control of
ISA bus.
DREQ0 – DREQ7 (Not include DREQ4)
DMA request signals. DRQ0 - DRQ3 are for 8 bits data
transfer. DRQ5 - DRQ7 are for 16 bits data transfer.
DACK0# - DACK7# (Not include DACK4#) (DACK#0-DACK#7)
DMA acknowledge signals. DACK0# - DACK3# are for 8
bits data transfer. DACK5# - DACK7# are for 16 bits data
transfer.
TC
E C B - 9 0 1 A
Quick Installation Guide - 33 -
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