Mitsubishi MELSEC-Q Series Programming Manual page 213

APPENDICES
Number Name
Operation output at
SM325
block STOP
SFC device clear
SM326
mode
Output mode at end
SM327
step execution
Clear processing
SM328 mode at arrival at end
step
Online change
SM329 (inactive block) status
flag
1: Available with the CPU module whose function version is B or later
5: Available with the universal model QCPU other than the Q00U(J), Q01U, Q02UCPU,
APP -4
Meaning
OFF: Coil output OFF
ON : Coil output ON
OFF: Clear device
ON : Preserves
device
OFF: HOLD step
output OFF
ON: HOLD step output
held
OFF: Clear processing
is performed
ON: Clear processing
is not performed
OFF : Not executed
ON : Being executed
whose serial number (first five digits) is "12052" or later. Available with the LCPU other
than the L02(S)CPU(-P), whose serial number (first five digits) is "15102" or later.
Explanation
Select whether the coil output of
the active step will be held or
not at a block STOP.
• As the default value, OFF
when coil output OFF is
selected for the output mode at
parameter block STOP, and
ON when coil output held is
selected.
• When this relay is OFF, the coil
outputs are all turned OFF.
• When this relay is ON, the coil
outputs are held.
• Select the device status when
the CPU is switched from
STOP to program write to
RUN. (All devices except the
step relay)
• When this relay is OFF, the
SC, SE or ST step that was
held when a transition
condition had been satisfied
turns OFF the coil output when
the end step is reached.
Select whether clear processing
will be performed or not when
active steps other than those
held exist in the block at the
time of arrival at the end step.
• When this relay is OFF, the
active steps are all ended
forcibly to end the block.
• When this relay is ON, the
execution of the block is
continued as is.
• When no active steps other
than those held exist at the
time of arrival at the end step,
the held steps are all ended to
end the block.
This relay indicates the
execution status of online
change (inactive block).
Corresponding CPU
Set by
(When set)
S (Initial), U
1
U
U
U
1
S (Status
change)
APP -4
5