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I
NTRODUCTION TO THE
• STRH (Store Register Halfword)
The STRB instruction stores the low byte of register R
instruction stores the low halfword of register R
6.1.1 Loading and Storing Multiple Registers
There are two instructions that allow loading of data into multiple registers, LDM (Load Multiple), and storing the
contents of multiple registers into memory, STM (Store Multiple). The memory operands must be in successive
word locations. These instructions are useful for two main purposes:
• transferring blocks of data between memory and processor registers, and
• saving data in registers on a stack, and then later restoring the registers from the stack
The address of the first word in memory is given in the base register, R
the contents of R
n
can be updated with the last address by specifying the Pre-indexed (!) addressing mode.
An instruction must specify the registers involved in the transfer. The registers must be listed in the assembly-
language instruction in a field enclosed by braces, but they do not have to be contiguous. A range of registers is
specified by listing the first and the last registers in the range, separated by a dash ( ). In the resulting machine
instruction, each register is identified by setting a corresponding bit in the field comprising the low-order 16 bits.
Registers are always stored by STM in the order from largest-to-smallest register-index (R15, R14, R13,
and loaded by LDM in the order from the smallest-to-largest register-index (R0, R1, R2,
The instruction must also indicate the direction in which memory addresses are computed. For block transfers there
are four possibilities for determining the addresses of consecutive data words. The address can be incremented or
decremented by 4 either before or after each data item is accessed. The desired action is specified by appending a
suffix to the OP-code mnemonic in the assembly-language instruction. The four suffixes are:
• IA – Increment After
• IB – Increment Before
• DA – Decrement After
• DB – Decrement Before
For example, the instruction
will load registers R4, R6, R7, R8 and R10. If the starting address in R3 is 1000, then the data loaded into the
registers will be from addresses 1000, 1004, 1008, 1012 and 1016, respectively. Because the Pre-indexed mode is
specified, the final contents of R3 will be 1020.
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into the memory byte specified by the address. The STRH
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LDMIA R3!, {R4, R6 R8, R10}
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FPGA T
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. Upon transferring the last word of data,
Intel Corporation - FPGA University Program
For Quartus Prime 16.1
. . .
, R0),
. . .
, R15).
November 2016
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