Assembler Directives - Intel ARM Cortex-A9 Introduction Manual

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I ARM P U I FPGA T
NTRODUCTION TO THE ROCESSOR SING NTEL OOLCHAIN
For Quartus Prime 16.1
The suffix AL (Always) causes the unconditional branch. The same effect is achieved if there is no suffix appended.
The Assembler interprets the instruction
B LABEL
as being the same as
BAL LABEL
6.12 Subroutine Linkage Instructions
Subroutine calls are achieved with the Branch and Link instruction
BL Destination
where the Destination is typically the label of the first instruction in the subroutine. In addition to behaving as a
Branch instruction, this instruction saves the return address (which is the address of the instruction that follows the
BL instruction) in the Link register, R14.
There is no specific return-from-subroutine instruction. The return from a subroutine can be performed by an in-
struction that loads the contents of R14 into R15, such as
MOV PC, LR
Since LR can hold only one return address, it follows that if nested subroutines are used it is necessary to save the
contents of R14, typically on the stack, prior to a nested subroutine call.
We should also mention that in the ARM environment, there is a convention that registers R0 to R4 are used to pass
parameters to a subroutine, while register R0 is used to return a result. If more than four parameters are needed, then
some of the parameters have to be passed via the stack.

7 Assembler Directives

Assembler directives provide information used by the assembler when assembling an application program. Different
assemblers often use different assembler directives. We will restrict our discussion to the assembler that is used by
the Intel FPGA Monitor Program. This assembler conforms to the widely used GNU Assembler, which is software
available in the public domain. Thus, the GNU Assembler directives can be used in ARM programs intended to be
used with the Intel FPGA Monitor Program.
Assembler directives begin with a period. We describe some of the more frequently used assembler directives below.
Intel Corporation - FPGA University Program 17
November 2016