Software Interrupt - Intel ARM Cortex-A9 Introduction Manual

I
NTRODUCTION TO THE
When an exception occurs in the User mode, the ARM processor switches into the corresponding exception mode
and automatically performs the following actions:
• Saves the contents of the Program Counter in the banked Link register, LR_mode.
• Saves the contents of the processor status register, CPSR, in the banked status register, SPSR_mode.
• Changes the mode bits in CPSR to denote the exception mode, and sets the interrupt-disable bits, I and F,
accordingly.
• Loads the Program Counter, PC, with a vector address for the exception that caused the action. At this address
in the exception table there is an instruction that is executed next.

11.1 Software Interrupt

A software interrupt, which is called a software exception in ARM literature, occurs when an SVC instruction is
encountered in a program. This instruction causes the processor to switch into Supervisor mode. The address of
the next instruction is saved in the banked register LR_svc and the contents of CPSR are saved in SPSR_svc. Then,
the address of entry 8 in the exception vector table is loaded into the Program Counter. A branch instruction at that
location leads to to the required exception-service routine.
Upon completion of the exception-service routine, a return to the interrupted program can be realized with the
instruction
Note that the suffix S in the OP-code mnemonic normally specifies that the Condition Code flags should be set.
However, when the destination register is PC, the suffix S causes the saved contents in register SPSR_mode, in this
case SPSR_svc, to be loaded into the processor status register CPSR. Since this instruction also loads the saved
return address into PC, a return to the interrupted program is completed.
A common use of the software interrupt is to transfer control to a different program, such as an operating system.
24
ARM
TABLE 4. Exception Vector Table
Address Exception
0x000 Reset
0x004 Unimplemented instruction
0x008 Software interrupt
0x00C Instruction access violation
0x010 Data access violation
0x018 IRQ
0x01C FIQ
®
P U I
ROCESSOR SING NTEL
Priority
1
6
5
2
4
3
MOVS PC, LR
FPGA T
OOLCHAIN
Mode entered
Supervisor
Undefined
Supervisor
Abort
Abort
IRQ
FIQ
Intel Corporation - FPGA University Program
For Quartus Prime 16.1
November 2016