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I
NTRODUCTION TO THE
Name
Offset:
Pre-indexed:
Post-indexed:
offset
shift
Consider the Load instruction, LDR, which loads a 32-bit operand into a register. The instruction
loads R2 from the address in R6 minus 8. The instruction
loads R2 from the address in R6 plus the hexadecimal number 0x200. The instruction
Intel Corporation - FPGA University Program
November 2016
ARM
TABLE 1. Memory addressing modes
Assembler syntax
n
immediate offset
[R
offset in R
m
[R
n
immediate offset
[R
n
offset in R
m
[R
n
immediate offset
[R
n
m
n
offset in R
[R
a signed number given in the instruction
direction #integer
where direction is LSL for left shift or LSR for right shift, and
integer is a 5-bit unsigned number specifying the shift amount
R
m
the magnitude in register R
from the contents of base register R
LDR R2, [R6, #0x200]
®
P
U
I
ROCESSOR
SING
Address generation
, #offset]
Address
, R
m
, shift]
Address
, #offset]!
Address
R
n
, R
m
, shift]!
Address
R
n
], #offset
Address
R
n
m
], R
, shift
Address
n
R
m
that is added to or subtracted
n
LDR R2, [R6, # 8]
LDR R2, [R6, R8]
FPGA T
NTEL
OOLCHAIN
n
[R
]
offset
[R
n
]
[R
m
] shifted
[R
n
]
offset;
address
[R
n
]
[R
m
] shifted;
address
[R
n
];
[R
n
]
offset
n
[R
];
n
m
[R
]
[R
] shifted
For Quartus Prime 16.1
5
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