Intel ARM Cortex-A9 Introduction Manual page 6

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I ARM P U I FPGA T
NTRODUCTION TO THE ROCESSOR SING NTEL OOLCHAIN
For Quartus Prime 16.1
loads R2 from the address obtained by subtracting the contents of R8 from the contents of R6.
The Pre-indexed mode is illustrated in
LDR R2, [R6, R8, LSL #4]!
which loads R2 from the location whose address is determined by shifting the contents of R8 to the left by 4 bit-
positions (which is equivalent to multiplying by 16) and adding the result to the contents of R6. Subsequently, the
generated address is loaded into R6.
An example of Post-indexed mode is
LDR R2, [R6], #20
where R6 contains the address of the location from which an operand is loaded into R2. Subsequently, the contents
of R6 are modified by adding to them the offset value 20.
Relative addressing can be used simply by specifying the address label associated with the desired memory location.
For example, if MEMLOC is the desired location, then the instruction
LDR R2, MEMLOC
will load the contents of memory location MEMLOC into register R2. The assembler will determine the immediate
offset as the difference between the address MEMLOC and the contents of the updated Program Counter. It will
generate the instruction
LDR R2, [R15, #offset]
This offset takes into account the fact that when the instruction is to be executed, the Program Counter will already
be incremented by 8, because the ARM processor will already have fetched the next instruction (due to pipelined
execution).
5.2 Format for Load and Store Instructions
The format for Load and Store instructions is shown in Figure 2. The operation code (OP-code) is provided in bits
27 to 20. The register R d , which is used as the destination in load instructions or as the source in store instructions,
is identified by bits 15 to 12. The base register, R n , is identified by bits 19 to 16. Bits 11 to 0 may contain a signed
12-bit offset or identify an index register. If an index register is used, its number, m , is given in the low-order four
bits of the instruction.
Observe, in Figure 2, that the high-order four bits denote a condition for the instruction. In ARM processors, most
instructions can be executed conditionally, as explained in Section 6.11.
6 Intel Corporation - FPGA University Program
November 2016