Intel ARM Cortex-A9 Introduction Manual page 16

I
NTRODUCTION TO THE
where a suffix is appended to indicate the condition on which a branch is to be taken. The branch target is typically
specified as a label. Relative addressing mode is used to define the target address. A 24-bit 2's-complement value
is given in the machine instruction to indicate the desired offset from the contents of the Program Counter, which is
computed by the Assembler. When the instruction is executed, this offset value is sign-extended to 32 bits. Then, the
resulting value is shifted left by two bit-positions because the branch target addresses are word-aligned. Finally, this
value is added to the updated contents of the Program Counter. Note that when any instruction is being executed,
the updated contents of PC will be the current contents of PC plus 8, because of the pipelined operation of the ARM
processor.
The branch instruction is executed conditionally, based on the current setting of the Condition Code flags. The
conditions that can be specified are given in Table 2. For example, the instruction
causes a branch to location LABEL if the Condition Code flag Z is equal to one when the instruction is being
executed.
Condition
field
b . . .
31
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
16
ARM
B{cond_suffix} LABEL
TABLE 2. Condition field encoding in ARM instructions
Condition Condition
suffix name
b
28
EQ Equal (zero)
NE Not equal (nonzero)
CS/HS Carry set/Unsigned higher or same
CC/LO Carry clear/Unsigned lower
MI Minus (negative)
PL Plus (positive or zero)
VS Overflow
VC No overflow
HI Unsigned higher
LS Unsigned lower or same
GE Signed greater than or equal
LT Signed less than
GT Signed greater than
LE Signed less than or equal
AL Always
not used
®
P U I
ROCESSOR SING NTEL
BEQ LABEL
FPGA T
OOLCHAIN
Condition Code
test
Z = 1
Z = 0
C = 1
C = 0
N = 1
N = 0
V = 1
V = 0
C Z 0
C Z 1
N V 0
N V 1
Z (N V) 0
Z (N V) 1
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