Kenwood DP-1100 B Service Manual page 76

2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION
Pin f u n c t i o n s
Pin No. Symbol
Positive input of built-in OP amp.
1 INA +
Forms the guard ring of INA— together with pin 3 (NC) fixed to approx. 1/2
Negative input of built-in OP amp.
The signal subject to resistance addition by charge pump circuit outputs UO and DO and
2
I N A -
TC9178F pin TMO is input.
Not used. This pin connected to pin INA + for giving isolation between pins I N A - and
3 NC
OUTA.
Output of built-in OP amp. Connected to pin I N A - through capacitor C and resistor R,
4 OUTA
forms a lag lead type filter to control VCO.
5 Negative voltage supply to analog circuit.
V E E 4
Not used. Connected to pin INA + for giving isolation between pin
6 NC
pins UO and DO.
Charge pump up signal output pin.
When signal PLCK obtained from 4-division of VCO frequency is phase delayed in rising
7 UO
edge against signal EFMI input, its " L " output duration is prolonged to make VCO fre­
quency higher. In phase lock, " L " level = 1/2 PLCK.
Charge pump down signal output pin. When signal PLCK obtained from 4-division of VCO
8 DO
frequency is phase advanced in rising edge against signal EFMI input, its " H " output dura­
tion is prolonged to make VCO frequency lower. In phase save, " H " level = 1/2 PLCK.
9 VCOI Input pin of VCO output signal. The signal subject to AC coupling by a capacitor is input.
10 GND GND pin for digital circuit
Input by which charge pump outputs UO and DO are made into high impedance.
11 G
When made " L " , high impedance mode is entered to hold the VCO frequency.
Output of data separation clock pulse generated from EFMI input signal in PLL circuit. This
output, obtained from 4-division of VCO frequency (17.3 MHz), is input to PLCK of
12 PLCK
C-MOS processor TC9178F.
The clock pulse is 4.32 MHz with duty ratio of 50.
Description
and each of output
T a b l e 2 - 3 - 2 A
D P - 1 1 0 0 B / D
Remarks
voltage.
VCCD
High impedance state ex­
cept during " L " direction.
High impedance state ex­
cept during " H " period
TTL level
C-MOS leve