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2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION
Pin f u n c t i o n s of external R A M I C 1 4 ( T C 5 5 1 4 P )
Pin
Port pin
Signal
No.
name
name
5
AO
AO
6
A1
A1
7
A2
A2
4
A3
A3
3
A4
A4
2
A5
A5
1
A6
A6
17
A7
A7
16
A8
A8
15
A9
A9
14
1/01
DO
13
I/02
D1
12
I/03
D2
11
I/04
D3
10
R/W
8
CE
9
GND
18
Power supply
V
D D
Control of external R A M I C 1 4 ( T C 5 5 1 4 P )
T h e external R A M is p r o v i d e d w i t h the f o l l o w i n g data storage
areas.
Different
data
are w r i t t e n
m i c r o p r o c e s s o r ports R 6 , P1 a n d R5 ( R 5 2 , R53) (address
d e s i g n a t i o n ) , port R7 (data I/O), port P2 (P20)
c o n t r o l ) or p o r t P2 (P21) (chip e n a b l e ) . (Refer to " P i n f u n c
t i o n s of I C I 5 " , T a b l e 2 - 3 - 1 A . )
(1)
Area of lead-in data (play start t i m e of e a c h t u n e a n d
r e a d - o u t start t i m e )
(2)
Area of t u n e N o . data ( T N O , X) of preset c h a n n e l s (CH 1
- 16)
(3)
Area of play t i m e data of e a c h preset c h a n n e l
(4)
Area of total play t i m e of e a c h c h a n n e l
First, t h e m e t h o d of access t o the area of read-in data (Area
(1)) is d e s c r i b e d .
A s s h o w n in T a b l e 2 - 3 - 6 A , IC14 is so c o n f i g u r e d t h a t r o w
address is d e s i g n a t e d by m i c r o p r o c e s s o r ports R52 a n d R 5 3 ,
LSB data of c o l u m n address by 4 ports R 6 , a n d MSB data of
c o l u m n address by 4 ports P 1 . H e r e , the m i c r o p r o c e s s o r is
p r o g r a m m e d so t h a t t h e binary c o n v e r s i o n value of the p o i n t
data (tune No.) w h i c h is r e a d , in reading the lead-in d a t a , is
set as c o l u m n address. A c o m p a c t disc c a n record up t o a
m a x i m u m of 9 9 t u n e s . T h u s , area of c o l u m n addresses H ' 0 1
t o H ' 6 3 ( H ' before the n u m b e r or a l p h a b e t m e a n s t h a t t h e y
are e x p r e s s e d in h e x a d e c i m a l ) is used as save area of lead-in
Initial
I/O
value
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
I
Address input from IC15 (TC4740N) (X32-1010-11)
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
Address input from IC15 (TC4740N) (X32-1010-11)
I
Data in/output from IC15 (TC4740N) {X32-1010-11)
I
I/O
Data in/output from IC15 (TC4740N) (X32-1010-11)
I/O
Data in/output from IC15 (TC4740N) (X32-1010-11)
I/O
Data in/output from IC15 (TC4740N) (X32-1010-11)
I
Read/write control signal input. " H " = Read, " L " = Write
I
Chip enable signal input (active " L " )
Ground
Ground
Power supply pin ( + 5 V)
Table 2 - 3 - 6 A
or
read
by c o n t r o l
of
( w r i t e / r e a d
Description
data (Area (1)). ( r e a d - o u t start t i m e data is saved in c o d e a d
dress H ' 6 4 . )
In c o m b i n a t i o n w i t h the c o l u m n address d e t e r m i n e d in this
m a n n e r , t h e 1 0 ' s digit of m i n u t e s data of play start t i m e is
saved in address 0 of the r o w address given by ports R 5 2 a n d
R 5 3 , the 1's digit of m i n u t e s data is saved in address 1 , t h e
1 0 ' s digit of s e c o n d s data in address 2 , a n d the 1 ' digit of
s e c o n d s data in location 3 . T h i s o p e r a t i o n t i m i n g is s h o w n in
Fig. 2 - 3 - 6 B . T h e r e m a i n i n g three areas ( 2 ) , (3) a n d (4) relate
w i t h preset c h a n n e l s . For c h a n n e l p r e s e t t i n g , a data save area
for 16 c h a n n e l s is n e e d e d . T o m e e t this n e e d , the area of c o l
u m n addresses H ' 8 0 - H ' F F is d i v i d e d into 16 s e c t i o n s . A s
s h o w n in Table 2 - 3 - 6 B , f o u r w o r d s of index LSB d a t a , index
MSB d a t a , T N O LSB data a n d T N O MSB data (Area (2)) are
saved in r o w address 0 in order f r o m the h e a d c o l u m n a d
dress of e a c h s e c t i o n , f o u r w o r d s of 1 's digit of s e c o n d s d a t a ,
1 0 ' s digit s e c o n d s d a t a , 1's digit of m i n u t e s data a n d 1 0 ' s
digit of m i n u t e s data (Area (3)) are in r o w address 1 , a n d five
w o r d s of 1 's digit of s e c o n d s d a t a , 1 0 ' s digit of s e c o n d s digit
d a t a , 1's digit of m i n u t e s d a t a , 1 0 ' s digit m i n u t e s data a n d
1 0 0 ' s digit of m i n u t e s data (Area (4)) are in r o w address 3 .
Fig. 2 - 3 - 6 C s h o w s this o p e r a t i o n t i m i n g .
D P - 1 1 0 0 B II
bitO
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bitO
bit 1
bit 2
bit 3
101
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