Silicon Laboratories C8051F500 User Manual page 17

Table 11. C8051F500 Target Board Pin Assignments and Headers (Continued)
P3.2 24
P3.3 23
P3.4 22
P3.5 21
P3.6 20
P3.7 19
P4.0 18
P4.1 17
P4.2 16
P4.3 15
P4.4 14
P4.5 13
P4.6 10
P4.7 9
/RST/C2CK 12
C2D 11
VIO 2
VREGIN 3
VDD 4
VDDA 5
GND 6
GNDA 7
*Note: Headers denoted by this symbol are not directly connected to the MCU pin; the connection might be via one or more
headers and/or pin-sharing resistor(s). See board schematic for details.
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
/RST C2CK
C2D
VIO
VREGIN
VDD
VDDA
GND
GNDA
Rev. 0.1
C8051F500DK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
/RST/C2CK P2[7], P2[5]*
C2D
VIO J24[4], J18[1], TB3[1]
VREGIN J24[2], P2[5]*, TB3[2]
VDD
VDDA
GND J1-J5[10], TB3[6]
VDD
J4[3]
J4[4]
J45]
J4[6]
J4[7]
J4[8]
J5[1]
J5[2]
J5[3]
J5[4]
J5[5]
J5[6]
J5[7]
J5[8]
P2[4]
J1-J5[9]
TB3[3]
TB3[4]
TB3[5]
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