Silicon Laboratories C8051F500 User Manual page 11

8.4. Switches and LEDs
Two push-button switches are provided on the target board for each MCU. Switch RESET_A is connected to the
/RST pin of the C8051F500. Switch RESET_B is connected to the /RST pin of the C8051F502. Pressing
RESET_A puts the C8051F500 device into its hardware-reset state, and similarly for RESET_B and the
C8051F502 MCU. Switches P1.4_A and P1.4_B are connected to the MCU's general purpose I/O (GPIO) pins
through headers. Pressing either one of these switches generates a logic low signal on the port pin. Remove the
shorting block from the header to disconnect these switches from the port pins. See Table 1 for the port pins and
headers corresponding to each switch.
Four LEDs are provided on the target board to serve as indicators. The red LED labeled PWR indicates presence
of power to the target board. The second red LED labeled COMM indicates if the CP2102 USB-to-UART bridge
(P5) is recognized by the PC. The green LED labeled with port pin name P1.3_A is connected to the C8051F500's
(Side A) GPIO pin P1.3 through the header J19. Remove the shorting block from the header to disconnect the LED
from the port pin. Similarly, the green LED named P1.3_B is connected to the C8051F502 (Side B) through the J11
header. See Table 1 for the port pins and headers corresponding to each LED.
8.5. Target Board Debug Interfaces (P2 and P3)
The debug connectors P2 (DEBUG_A) and P3 (DEBUG_B) provide access to the debug (C2) pins of the
C8051F500 and C8051F502. The debug connectors are used to connect the Serial Adapter or the USB Debug
Adapter to the target board for in-circuit debugging and Flash programming. Table 2 shows the DEBUG pin
definitions.
Side A - C8051F500
Pin #
1
2, 3, 9
4
5
6
7
8
10 USB Power (+5VDC from P2)
Table 1. Target Board I/O Descriptions
Description
RESET_A
RESET_B
P1.4_A Switch
P1.4_B Switch
P1.3_A LED
P1.3_B LED
Red LED (PWR)
Red LED (COMM)
Table 2. DEBUG Connector Pin Descriptions
Description
Not Connected
GND (Ground)
C2D_A
/RST (Reset)
Not Connected
/RST/C2CK_A
Not Connected
I/O Header(s)
Reset (Side A)
Reset (Side B)
P1.4 (Side A)
P1.4 (Side B)
P1.3 (Side A)
P1.3 (Side B)
Power
COMM Active
Side B - C8051F502
Pin # Description
1 Not Connected
2, 3, 9 GND (Ground)
4 P3.0_C2D_B
5 /RST_B (Reset)
6
7 /RST/C2CK_B
8 Not Connected
10 Not Connected
Rev. 0.1
C8051F500DK
none
none
J191–2]
J11[1–2]
J19[3–4]
J11[3–4]
none
none
P3.0_B
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