Silicon Laboratories C8051F500 User Manual page 13

8.8. LIN Interface and Network (TB1)
Both MCUs on the target board are connected to LIN transceivers through headers. These headers assume that
the MCU's crossbars are configured to put the LIN TX and RX pins on port pins P1.0 and P1.1 respectively. See
the C8051F50x data sheet for crossbar configuration. The C8051F500 (Side A) is connected to the T1 transceiver
through the J17 header and the C8051F502 (Side B) is connected to the T2 transceiver through the J26 header.
The two LIN transceivers are connected to each other and form a LIN network. Other external devices can be
connected to the LIN network through the TB1 interface. The TB1 interface also provides the option for connecting
an external power source so that all LIN transceivers can use the same source voltage. This source voltage can
also be used to power the target board. If an external voltage source is not provided, the LIN transceivers use the
12V provided through the P4 wall-wart connector. See Section 8.2. for more power option details. The shorting
block positions for connecting the MCUs to the LIN transceivers are listed in Table 6. The pin connections for the
external LIN devices are listed in Table 7.
Table 6. LIN Interface Headers (J17 and J26) Description
Table 7. TB1 External LIN Interface Header Description
8.9. Port I/O Connectors (J1-J5 and J27-J29)
Each of the parallel ports of the C8051F500 (Side A) and C8051F502 (Side B) has its own 10-pin header
connector. Each connector provides a pin for the corresponding port pins 0-7, +5V VIO, and digital ground. The
same pin-out is used for all of the port connectors.
Header Pins LIN0 Pin Description
J17[9–10] LIN_TX (P1.0_A)
J17[11–12] LIN_RX (P1.1_A)
J26[5-6] LIN_TX (P1.0_B)
J26[7-8] LIN_RX (P1.1_B)
Pin # Pin Description
1
2
3
Table 8. Port I/O Connector Pin Description
Pin # Pin Description
1
2
3
4
5
6
7
8
9
10
Rev. 0.1
C8051F500DK
+LIN_V
LIN_OUT
GND
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pn.7
+5V (VIO)
GND (Ground)
13