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11
(1) ADnCSPD (A-Dn conversion speed select) bit (D9)
This bit selects the A-D conversion speed when the A-Dn converter is operating in scan mode.
Setting this bit to 0 selects normal speed; setting this bit to 1 selects double speed.
Note: Because the A-Dn conversion speed during scan mode is determined by a combined use
of this ADnCSPD bit and the A-Dn Conversion Speed Control Register ADnCVSD bit,
make sure the ADnCSPD and ADnCVSD bits both are set.
(2) ANnSCAN (A-Dn scan loop select) bits (D12-D15)
These bits select a range of channels by channel number beginning with the channel ADnIN0
which are to be operated on during scan mode operation with the A-Dn converter.
(For details about the scan loop configuration by specified channel numbers, see Table 11.1.2.)
When the ANnSCAN (A-Dn scan loop select) bits are read out during scan operation, they serve
as status bits indicating the channel being converted.
When read during single mode, these bits always show the value "B'0000."
If these bits are read when the A-D conversion is stopped by setting the Scan Mode Register 0
ADnCSTP (A-Dn conversion stop) bit to 1, they show the value of the channel that has been
canceled of A-D convert operation.
Also, when read during single mode conversion in special operation mode "Forcibly execute
single mode during scan mode operation," they show the value of the channel that has been
canceled of A-D convert operation in the middle of scan.
11.2 A-D Converter Related Registers
11-32
A-D CONVERTERS
Rev.1.0
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