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32173
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Mitsubishi 32173 manual available for free PDF download: User Manual
Mitsubishi 32173 User Manual (874 pages)
M32R series
Brand:
Mitsubishi
| Category:
Computer Hardware
| Size: 3.64 MB
Table of Contents
Table of Contents
5
Chapter 1 Overview
21
Overview
21
M32R Family CPU Core
22
Built-In Multiply-Accumulate Operation Function
23
Built-In Flash Memory and RAM
23
Built-In Clock Multiplier Circuit
24
Built-In Powerful Peripheral Functions
24
Built-In Full-CAN Function
25
Two Built-In D-A Converters
25
Built-In Timer/Arithmetic Circuits for PD (Phase Digital) Sensors
26
Built-In Debug Function
26
Block Diagram
27
Pin Functions
30
Pin Layout
38
Chapter 2 Cpu
45
CPU Registers
45
General-Purpose Registers
45
Control Registers
47
Processor Status Word Register: PSW (CR0)
48
Condition Bit Register: CBR (CR1)
49
Interrupt Stack Pointer: SPI (CR2)
49
User Stack Pointer: SPU (CR3)
49
Backup PC: BPC (CR6)
49
Accumulator
50
Program Counter
50
Data Formats
51
Data Types
51
Data Formats
52
Chapter 3 Address Space
59
Outline of the Address Space
59
Operation Modes
59
Internal ROM and External Extended Areas
59
Internal ROM Area
60
External Extended Area
60
Internal RAM and SFR Areas
67
Internal RAM Area
67
SFR (Special Function Register) Area
67
EIT Vector Entry
93
ICU Vector Table
94
Precautions on Address Space
96
Chapter 4 Eit
97
Outline of EIT
97
EIT Events
99
Exceptions
99
Interrupts
99
Trap
99
EIT Processing Procedure
100
EIT Processing Mechanism
102
Accepting EIT Events
103
Saving and Restoring PC and PSW
104
EIT Vector Entry
106
Exception Handling
107
Reserved Instruction Exception (RIE)
107
Address Exception (AE)
109
Interrupt Handling
111
Reset Interrupt (RI)
111
System Break Interrupt (SBI)
112
External Interrupt (EI)
114
Trap Handling
116
Trap (TRAP)
116
EIT Priority
118
Example of EIT Processing
119
Precautions on EIT
121
Outline of the Interrupt Controller (ICU)
124
Chapter 5 Interrupt Controller (Icu)
125
Interrupt Sources of Internal Peripheral I/Os
126
ICU Related Registers
128
Interrupt Vector Register
129
Interrupt Mask Register
130
SBI (System Break Interrupt) Control Register
131
Interrupt Control Registers
132
ICU Vector Table
136
Description of Interrupt Operation
139
Accepting Interrupts from Internal Peripheral I/O
139
Processing of Internal Peripheral I/O Interrupts by Handler
142
Description of System Break Interrupt (SBI) Operation
144
Accepting SBI Interrupt
144
SBI Processing by Handler
144
Chapter 6 Internal Memory
145
Outline of the Internal Memory
145
Internal RAM
145
Internal Flash Memory
145
Internal Flash Memory Related Registers
145
Flash Mode Register
148
Flash Status Registers
149
Flash Control Registers
152
Virtual-Flash L Bank Registers
158
Virtual-Flash S Bank Registers
159
Programming the Internal Flash Memory
160
Outline of Flash Memory Programming
160
Controlling Operation Modes During Flash Programming
166
Procedure for Programming the Internal Flash Memory
169
Flash Programming Time (Reference Data)
180
Boot ROM
181
Virtual-Flash Emulation Function
182
Virtual-Flash Emulation Areas
184
Transition to Virtual-Flash Emulation Mode
189
Application Example for Virtual-Flash Emulation Mode
190
Connecting a Serial Programmer
192
Precautions on Rewriting Flash Memory
194
Chapter 7 Reset
195
Outline of Reset
195
Reset Operation
195
Power-On Reset
196
Reset During Operation
196
Reset Vector Movement During Flash Rewrite
196
Internal State Immediately after Reset
197
Precautions to be Taken Immediately after Reset
199
Chapter 8 Input/Output Ports and Pin Functions
201
Outline of Input/Output Ports
201
Selecting Pin Functions
201
Input/Output Port Related Registers
201
Port Data Registers
208
Port Direction Registers
209
Port Operation Mode Registers
210
Port Peripheral Circuits
231
Precautions on Input/Output Ports
239
Chapter 9 Dmac
241
Outline of DMAC
241
DMAC Related Registers
241
DMA Channel Control Registers
247
DMA Request Extended Cause Register
258
DMA Software Request Generation Registers
269
DMA Source Address Registers
270
DMA Destination Address Registers
271
DMA Transfer Count Registers
272
DMA Interrupt Request Status Registers
273
DMA Interrupt Mask Registers
275
Functional Description of DMAC
279
Cause of DMA Request
279
DMA Transfer Processing Procedure
289
Starting DMA
290
Priority of DMA Channels
290
Gaining and Releasing Control of the Internal Bus
291
Transfer Unit
291
Address Space
292
Transfer Operation
292
End of DMA and Interrupt
295
Register Status after End of DMA Transfer
295
Precautions on Using DMAC
296
Outline of the Input/Output Timers
300
Chapter 10 Input/Output Timers
306
Common Timer Unit
306
Register Map of the Common Timer Unit
306
Prescaler Unit
308
Input Processing Control Unit
309
Output Flip-Flop Control Unit
318
Interrupt Control Unit
322
TMS (Input Related 16-Bit Timers)
341
Outline of the TMS
341
Functional Outline of the TMS
341
TMS Related Register Map
343
TMS Control Register
344
TMS Counter (TMS0CT)
345
TMS Measure Registers (TMS0MR3~0)
346
TMS Old Measure Registers (TMS0OLDMR3~0)
347
Operation of TMS Measure Input
348
TML (Input Related 32-Bit Timers)
350
Outline of the TML
350
Functional Outline of the TML
351
TML Related Register Map
352
TML Control Register
353
TML Counters
354
TML Measure Registers
355
TML Old Measure Registers
356
Operation of TML Measure Input
357
TID (Input Related 16-Bit Timers)
359
Outline of the TID
359
TID Related Register Map
361
TID Control & Prescaler Enable Registers
362
TID Counters (TID0CT and TID1CT)
364
TID Reload Registers (TID0RL and TID1RL)
365
Outline of each TID Operation Mode
366
TOM (Output Related 16-Bit Timers)
373
Outline of the TOM
373
Outline of each TOM Operation Mode
375
TOM Related Register Map
377
PWM Output Disable Registers
380
PWM Output Disable Control Registers
382
TOM Control Registers
386
TOM Counters
388
TOM Reload 0 Registers
390
TOM Reload 1 Registers
392
TOM Enable Protect Registers
394
TOM Count Enable Registers
396
TID Control & Prescaler Enable Registers
398
Operation of TOM in PWM Output Mode
401
Operation of TOM in Single-Shot Output Mode
405
Operation of TOM in Single-Shot PWM Output Mode
407
(Without Correction Function)
408
Operation of TOM in Successive Output Mode
409
TOM Output Disable Function
411
Example for Using the TOM in Motor Control Applications
414
Chapter 11 A-D Converters
417
Outline of the A-D Converters
417
Conversion Modes
418
Operation Modes
418
Special Operation Modes
418
Interrupt and DMA Transfer Requests by A-D Converters
430
A-D Converter Related Registers
431
A-D Single Mode Registers 0
435
A-D Single Mode Registers 1
439
A-D Scan Mode Registers 0
442
A-D Scan Mode Registers 1
446
A-D Conversion Speed Control Registers
449
A-D Digital Input Control Registers
451
A-D Successive Approximation Registers
452
A-D Comparate Data Registers
454
10-Bit A-D Data Registers
456
8-Bit A-D Data Registers
458
Functional Description of the A-D Converters
460
How to Find Analog Input Voltages
460
A-D Conversion of Successive Approximation Method
461
Comparator Operation
463
Calculating the A-D Conversion Time
464
Definition of the A-D Conversion Accuracy
468
Precautions on Using the A-D Converters
470
Chapter 12 Serial I/O
471
Outline of Serial I/O
471
Serial I/O Related Registers
471
SIO Interrupt Related Registers
480
SIO Interrupt Control Registers
482
SIO Transmit Control Registers
489
SIO Transmit/Receive Mode Registers
491
SIO Transmit Buffer Registers
494
SIO Receive Buffer Registers
495
SIO Receive Control Registers
496
SIO Baud Rate Registers
499
Transmit Operation in CSIO Mode
501
Setting the CSIO Baud Rate
501
Initial Settings for CSIO Transmission
502
Starting CSIO Transmission
504
Successive CSIO Transmission
504
Processing at End of CSIO Transmission
505
Transmit Interrupt
505
Transmit DMA Transfer Request
505
Typical CSIO Transmit Operation
507
Receive Operation in CSIO Mode
509
Initial Settings for CSIO Reception
509
Starting CSIO Reception
511
Processing at End of CSIO Reception
511
About Successive Reception
512
Flags Indicating the Status of CSIO Receive Operation
513
Typical CSIO Receive Operation
514
Precautions on Using CSIO Mode
516
Transmit Operation in UART Mode
518
Setting the UART Baud Rate
518
UART Transmit/Receive Data Formats
519
Initial Settings for UART Transmission
521
Starting UART Transmission
523
Successive UART Transmission
523
Processing at End of UART Transmission
524
Transmit DMA Transfer Request
524
Typical UART Transmit Operation
526
Receive Operation in UART Mode
528
Initial Settings for UART Reception
528
Starting UART Reception
530
Processing at End of UART Reception
530
Typical UART Receive Operation
532
Fixed Period Clock Output Function
534
Precautions on Using UART Mode
535
Chapter 13 Can Modules
537
Outline of the CAN Modules
537
CAN Module Related Registers
537
CAN Control Registers
549
CAN Status Registers
553
CAN Extended ID Registers
557
CAN Configuration Registers
558
CAN Time Stamp Count Registers
561
CAN Error Count Registers
562
CAN Baud Rate Prescalers
563
CAN Interrupt Related Registers
564
CAN Mask Registers
575
CAN Message Slot Control Registers
579
CAN Message Slots
584
CAN Protocol
614
CAN Protocol Frames
614
Initialization of the CAN Module
617
Initializing the CAN Module
617
CAN Timing
620
Transmitting Data Frames
621
Data Frame Transmission Procedure
621
Data Frame Transmit Operation
623
Transmit Abort Function
624
Receiving Data Frames
625
Data Frame Reception Procedure
625
Data Frame Receive Operation
627
Reading out a Received Data Frame
629
Transmitting Remote Frames
631
Remote Frame Transmission Procedure
631
Remote Frame Transmit Operation
633
Reading out a Received Data Frame When Set for Remote Frame Transmission
636
Receiving Remote Frames
638
Remote Frame Reception Procedure
638
Remote Frame Receive Operation
640
Chapter 14 Real-Time Debugger (Rtd)
643
Outline of the Real-Time Debugger (RTD)
643
Pin Function of the RTD
643
Functional Description of the RTD
643
Outline of RTD Operation
646
Operation of RDR (Real-Time RAM Content Output)
647
Operation of WRR (RAM Content Forcible Rewrite)
649
Operation of VER (Continuous Monitor)
651
Operation of VEI (Interrupt Request)
652
Operation of RCV (Recover from Runaway)
653
Method to Set a Specified Address When Using the RTD
654
Resetting the RTD
655
Typical Connection with the Host
656
Chapter 15 Pd Module
659
Outline of the PD Module
659
PD Module Related Registers
659
Prescaler Unit
665
DACNT Reload Register
668
TIN Input Processing Control Register
669
TIN Interrupt Control Register
671
TIN Interrupt Status Register
672
DACNT Control Register
674
TPD Control Register
675
DACNT Counter
676
TPD Counter
677
TPD Measure Registers
678
PD Calculation Interrupt Control Register
680
PD Calculation Interrupt Status Register
681
Position Detection Accuracy Select Register
683
TEP Control Registers
684
TEP Counters
686
PD Data Updating Disable Event Select Registers
688
PD Data Updating Control Registers
689
ABD Mask Registers
690
S Error Detection Range Select Registers
691
ABD Compare Registers
692
PITCH Compare Registers
693
FDLT Registers
694
PITCHLT Registers
695
ABDLT Registers
696
RSUMLT Registers
697
SSLT Registers
698
Initialization for PD Sensor Support
701
Precautions on Using the PD Module
702
Chapter 16 D-A Converters
703
Outline of the D-A Converters
703
D-A Converter Related Registers
707
Prescaler Unit
710
DACNT Control Register
712
DACNT Reload Register
713
DACNT Counter
713
D-A Control Register
714
D-A Conversion Registers
715
D-A0 Data Registers
716
Functional Description of the D-A Converters
717
Single Mode
717
Chapter 17 External Bus Interface
719
External Bus Interface Related Signals
719
Read/Write Operations
719
Bus Arbitration
719
Example for Connecting External Extension Memory
719
Chapter 18 Wait Controller
745
Outline of the Wait Controller
745
Wait Controller Related Registers
745
Wait States Control Register
751
Typical Operation of the Wait Controller
752
Chapter 19 Ram Backup Mode
767
Outline
767
Example of RAM Backup When Power Is down
767
Outline
768
Normal Operating State
769
RAM Backup State
770
Example of RAM Backup for Saving Power Consumption
771
Normal Operating State
772
RAM Backup State
773
Precautions to be Observed at Power-On
774
Exiting RAM Backup Mode (Wakeup)
775
Chapter 20 Oscillation Circuit
777
Oscillator Circuit
778
Example of an Oscillator Circuit
778
System Clock Output Function
779
Oscillation Stabilization Time at Power-On
780
Clock Generator Circuit
781
Chapter 21 Jtag
783
Outline of the JTAG
783
Configuration of the JTAG Circuit
783
JTAG Registers
783
Instruction Register (JTAGIR)
786
Data Registers
787
Basic Operation of the JTAG
788
Outline of the JTAG Operation
788
IR Path Sequence
788
DR Path Sequence
788
Examining and Setting Data Registers
794
Boundary Scan Description Language
796
Precautions on Board Design When Connecting the JTAG
819
Processing Pins When Not Using the JTAG
821
Chapter 22 Power-Up/Power-Shutdown Sequence
823
Configuration of the Power Supply Circuit
823
Power-On Sequence
823
Power-On Sequence When Not Using RAM Backup
825
Power-On Sequence When Using RAM Backup
826
Power-Shutdown Sequence
827
Power-Shutdown Sequence When Not Using RAM Backup
827
Power-Shutdown Sequence When Using RAM Backup
828
Chapter 23 Electrical Characteristics
831
Absolute Maximum Ratings
831
Recommended Operating Conditions
831
DC Characteristics
831
Electrical Characteristics
831
Flash Related Electrical Characteristics
839
A-D Conversion Characteristics
840
D-A Conversion Characteristics
841
AC Characteristics
842
Timing Requirements
842
Switching Characteristics
846
AC Characteristics
846
Chapter 24 Standard Characteristics
857
A-D Conversion Characteristics
857
Specifications
859
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