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11
(1) ADnSMSL (A-Dn conversion mode select) bit (D8)
This bit selects A-D conversion mode when the A-Dn converter is operating in single mode.
Setting this bit to 0 selects A-D conversion mode; setting this bit to 1 selects comparator mode.
(2) ADnSSPD (A-Dn conversion speed select) bit (D9)
This bit selects the A-D conversion speed when the A-Dn converter is operating in single mode.
Setting this bit to 0 selects normal speed; setting this bit to 1 selects double speed.
Note: Because the A-Dn conversion speed during single mode is determined by a combined
use of this ADnSSPD bit and the A-Dn Conversion Speed Control Register ADnCVSD
bit, make sure the ADnSSPD and ADnCVSD bits both are set.
(3) ANnSEL (analog input pin select) bits (D12-D15)
These bits select an analog input pin when the A-Dn converter is operating in single mode. The
channel selected with this bit is the target channel on which A-D conversion or comparate
operation is performed. When read, this bit shows the value that has been written to it.
11.2 A-D Converter Related Registers
11-25
A-D CONVERTERS
Rev.1.0
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