Mitsubishi 32172 User Manual page 280

9
Table 9.3.3 Causes of DMA Request on DMA1 and the Timing at Which Requests are Generated
REQSL1 Causes of DMA Request
0 0 Software start
0 1 Extended request cause
1 0 Timer (TOM01_udf)
1 1 One DMA0 transfer completed
Table 9.3.4 DMA Request Extended Causes on DMA1 and the Timing at Which Requests are Generated
REQESEL1 DMA Request Extended Cause
0000 All DMA1 transfers completed
0001 TID0_udf,ovf
0010 TID1_udf,ovf
0011 TIN16 input signal
0100 TIN17 input signal
0101 TOM02_udf
0110 Serial I/O-4 (reception completed) When serial I/O-4 reception is completed
0111 One DMA9 transfer completed
1000 PD_CMP0
1001 PD_CMP1
Note: The DMA request extended causes are effective only when "Extended request cause" is selected with
the DMA1 Channel Control Register REQSL1 bits.
9.3 Functional Description of DMAC
DMA Request Generation Timing
When any data is written to the DMA1 Software Request
Generation Register
–
When TOM01 timer underflows
When one transfer on DMA0 is completed (cascade mode)
DMA Request Generation Timing
When all transfers on DMA1 are completed (cascade mode)
When TID0 timer underflows or overflows
When TID1 timer underflows or overflows
When the timer's TIN16 input signal is generated
When the timer's TIN17 input signal is generated
When TOM02 timer underflows
When one transfer on DMA9 is completed (cascade mode)
When absolute data comparison on PD module channel 0
matched
When absolute data comparison on PD module channel 1
matched
9-40
DMAC
Rev.1.0