Interrupt Mask Register - Mitsubishi 32172 User Manual

5

5.3.2 Interrupt Mask Register

Interrupt Mask Register (IMASK)
D0
D Bit Name
0-4 No functions assigned
5-7 IMASK (interrupt mask)
The Interrupt Mask Register (IMASK) is used to set an interrupt mask to be compared with the
priority level that has been set for each interrupt source (i.e., the Interrupt Control Register ILEVEL
bit) to determine whether or not to accept the interrupt request.
When the Interrupt Vector Register (IVECT) described above is read out, a new mask value
(NEW_IMASK) is set in this IMASK Register.
Upon writing to the IMASK Register, operations (1) to (2) below are automatically performed in
hardware.
(1) Negate the interrupt request (EI) sent to the CPU core
(2) Activate the ICU's internal sequencer to start internal processing (interrupt priority
resolution)
Do not write to the Interrupt Mask Register (IMASK) in other than the EIT handler
(unless the PSW Register IE bit is disabled).
1 2 3
Function
000: Disables maskable interrupt
001: Enables level 0 interrupt to be accepted
010: Enables level 0-1 interrupts to be accepted
011: Enables level 0-2 interrupts to be accepted
100: Enables level 0-3 interrupts to be accepted
101: Enables level 0-4 interrupts to be accepted
110: Enables level 0-5 interrupts to be accepted
111: Enables level 0-6 interrupts to be accepted
CAUTION
INTERRUPT CONTROLLER (ICU)
4 5
IMASK
5-8
5.3 ICU Related Registers
<Address: H'0080 0004>
6 D7
<When reset: H'07>
R W
0 –
Rev.1.0