Output Flip-Flop Control Unit - Mitsubishi 32172 User Manual

10

10.2.4 Output Flip-flop Control Unit

The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. There are
following output flip-flop control registers.
• F/F Protect Register 0 (FFP0)
• F/F Protect Register 1 (FFP1)
• F/F Data Register 0 (FFD0)
• F/F Data Register 1 (FFD1)
Table 10.2.1 below lists the timing at which a signal for the output flip-flop is generated by each
timer.
Table 10.2.1 Timing at Which Signal for Output Flip-flop is Generated by Each Timer
Timer Mode
TMS (16-bit measurement input)
TML (32-bit measurement input)
TID Fixed period count mode
Event count mode
Multiply-by-4 event count mode
Up/down event count mode
TOM PWM output mode
Single-shot PWM output mode
Single-shot output mode
Successive output mode
INPUT/OUTPUT TIMERS
Timing at which signal for output flip-flop is generated
No signal generating function
No signal generating function
No signal generating function
No signal generating function
No signal generating function
No signal generating function
When counter is enabled or underflows
When counter underflows
When counter is enabled or underflows
When counter is enabled or underflows
10-20
10.2 Common Timer Unit
Rev.1.0