Wavetek ANT-20 Operating Manual page 15

ANT-20/ANT-20E
Fig. I-6
The "Signal Structure" VI can be used to set the appropriate mapping for concatenated
containers for the transmitter (Tx) and receiver (Rx).
The following VIs can be used for tests after the settings are made:
• Performance Analyzer
• Anomaly/Defect Analyzer
• Anomaly/Defect Insertion
• Overhead Analyzer
• Overhead Generator
• Pointer Analyzer
• Pointer Generator
• Jitter Generator/Analyzer
• ATM Signal Structure
• ATM Traffic Analyzer
• ATM Background Load Generator
The "OC-48c/STM-16c ERROR TEST (BULK)", "OC-12c/STM-4c ERROR TEST (BULK)" and
"OC-12c/STM-4c ATM TESTING" options provide test functions for contiguous concatenation
mapping.
With the "OC-48c/STM-16c ERROR TEST (BULK)" and "OC-12c/STM-4c ERROR TEST
(BULK)"options, a bulk signal is mapped into the concatenated containers. With the "OC-12c/
STM-4c ATM TESTING" option, cells are mapped into the containers.
By combining the "OC-12c/STM-4c ATM TESTING" option with the ATM module and the "Jitter
Generator/Analyzer 622 Mbit/s", it is possible to demonstrate the conformance of ATM network
elements to the jitter requirements of ITU-T, Bellcore and ANSI.
Introduction
Contiguous concatenation, STS-12c SPE or VC-4-4c in OC-48c or STM-16c
Concatenation Options
I-7