5.3.1
Level Translator Interfaces
Two different level translator circuits are implemented in GR64.
interface is used on all level-translated IO with the exception of the I2C signals, SDA
& SCL.
5.3.1.1
Common Level Translator Interface
The common level translator used within the GR64 uses a Maxim MAX3001E. The
level translators have built-in ESD protection to ±15kV (HBM).
Figure 8: Common level translator circuitry using MAX3001
VREF represents the application side while VL represents the Wireless CPU side.
Table 4: Level Translator I/O Logic Levels
Parameter
IO input voltage high threshold (V
IO input voltage low threshold (V
IO output voltage high threshold (V
IO output voltage low threshold (V
Rise and Fall time (C
IO input impedance (pulled to VREF or GND)
GR64 Integrators Manual
Page: 34/104
)
IHC
)
ILC
)
OHC
)
OLC
= 15pF)
L
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The 'common'
Min
Nom
Max
0.75*VREF
VREF
0
0.3
0.67*VREF
VREF
0
0.4
15
6
Unit
V
V
V
V
ns
kohm
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