General Electrical And Logical Characteristics - Wavecom GR64 GSM/GPRS Integrator's Manual

5.3

General Electrical and Logical Characteristics

The core digital IO is based upon 1.8V technology in the Baseband chipset. All
external IO signals undergo bi-directional level shifting on the physical Wireless CPU
to provide flexibility to users of different voltage technology. An internal core IO
regulator is used as a reference for the Wireless CPU-side logic, whilst the application
(host-side) reference is fed by VREF in one of two implementations.
In order to provide legacy users a migration path to GR64, the Wireless CPU IO is
made compatible with 2.8V (or level-adapted 3.0V) controllers, popular in older
technology applications.
GR64001 and all its SW-variants. In these products the 2.8V VREF is derived from an
internal voltage regulator, distributed to the host-side level translators and also
output on the VREF signal pin.
The arrangement differs in non-legacy variant GR64 product GR64002 and all its SW-
variants. In these products the internal voltage regulator is disconnected and the
user application provides the VREF as a reference to the host-side level translators.
The range of VREF voltages is specified in section 5.6.
NOTE
GR64 Integrators Manual
Page: 33/104
This arrangement is implemented in variant product
Many of the signals indicated in Table 2 are high-speed CMOS logic
inputs or outputs powered by the 1.8V internal core regulators, and
then subsequently level shifted at the system interface. All serial
interfaces and general purpose IO fall in to this category.
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