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and more about Sharp
PC-1500
at http://www.PC-1500.info
CLI
SDI
no
3-4-4.
Reset
0
2 3 4 5 6 7
11'1
se(ia1
receive
~
A'>~~~~~~~~~~-'
1
Reset as
it
\vent
into
serial
data
receive.
Reset
as the
CPU
read
the
seda1
data.
When
the R
ES
ET
line
is
kept in
..
, .. at
least
for
three
<IOS
clock
cyd cs. it
causes
internal
reset
.
by
which all
internal
rcgistcn<
arc clea red
to
"0"
a nd
ports
PA and PB go into
the
input
n1ode.
·111e
divider.
hovicver.
\viii
not
be
reset.
Terminal
states
after
the reset arc
as
shown
in
Table
below.
Pin
name
In/Out
Stace after
reset
00-
01
l
o/Out
High
impedance
PAO-·PA7
..
..
PBO-
PB7
..
..
l -
PCO-
PC7
Out
I
Lov: 1c
... e1
WAIT
..
(NOTE)
DMEO
..
..
DM
Et
..
..
INT
"
L0\•1
leve
l
SDO
In/O
ut
High
level
CLO
..
Lo\•1
le\lel
NOTE:
WAIT.
DM
EO. and
OM Et are output
dependent
of WO.
MEO, W1
,
and
MEl
and do
not
have any co
nnection
,.,ith
reset.
77
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