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Q)
Timer
interrupt
When interrupt
i' rcquc.1cd
from the timer.
it
sc1s
1he
OipOop IRI ac1h
c.
If 1hc
interrupt
enable
IE
i,
aeti\e
al
1hi>
poinl.
1he
CPU
stan> executing
the mtcrrup1
processing after
conlplc1ic1n
t>(
current
in~truction
cxttuti<>n. and IR I ''ill
be reset in
a course of
the
interrupt prcH:c:-.."'
.
\\,.ht:n interrupt
i!!i
requested
\\flilc
IF
i~
inacti\'c,
the lntcrrupt
\\'ill
he.:
ignored
C\Crl
1hough
IR
I
is
set.
Timer
interrupt
processing sequence
Return to main routine
I
•
$
~
· -~
0
•I(
0
•• ,
....
.
$
~
I
•
$
f
li
•
$
5
I
•$
1rr•11
...
H
"
fl»•·
·
l'l
"fl1
e
l~TI
instruction is
u~d
for
ret urning
lr<nn
thc
intC'rrupt
proccs~ing
rou1i11..: to 1hc
n1ain
r<>utine.
lk."(<:'u~
the
content~
of
the
T rcgi,tcr
and the progrJOl
counter
;.ire
st<1rc<l in
the 'tack
at
the
beginning of the interrupt prOCC>sing
routine.
the contents
of
the
T register in
the stack
n:tums
by the
RT
t
instruction.
Sin<-.:
the
interrupt enable
ll;ig IE
i, con1ained in the T
rcgis1cr.
1he
contcnl>
ol
IF.
irnmcdiatcly octore
the in1ernipt
return>
b) the
RTI
in
~ truction.
To disable 1naskc.
1 bl..:-
or tinter intc1rup1
b) the
n1ain
roulinc
after
returning
triun
the
interrupt processing
r<n1t
inc.
1
hi.;
bi
l
in
1h...:
:ila<.:k
corresponding
to the tlag
IE
n1u~t
be
l'C'\l:t
.
Priority
order of
interrupts
(
I
)
Non-maskable
i111orr11p1
rc,p<>rlCI>
to
th('
interrupt
r..::qul·~t
\\h.-tlC\Cr
the
Cl)U
in1ern;.1l
s1:uc
nta~
be.
,\lso.
it
n.-sponds
in
tl.e
fi()t
pri<>rit~
e'en
durin.g
c,
, ccution
of
interrupt
routine
by
c>1hcr in1crrupt.
-··
·
- · i
~..........,
-....-
~··'
l~
Do not sale this PDF !!!
..
·~-
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,,.,_
...
19
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