Advertisement
76
All
and
more about
Sharp
PC-1500
at http://www.PC-1500.info
0
Wait time
of
1/0
port
controller
itself
When
the
CPU
accesses
the
1/
0
pon
controller. wait
of a
single
CPU
machine
cycle
is
auwmatically
applied
.
If the WO
and WI
is in
the \\".tit slate
when
the CP
U
accessed
the
1/
0
port
contr oller.
\\iait
ends
in
one
cycle.
NO
TE:
When
there is
no
\•1ait
condition
ir)
WO
and \V1
.
the
same
\'l3vefoun
as
MEO
ar1d
ME
1
are
sent on
DMEO
and
0ME1.
'
.
t<-
i
~:
'
'
•
! \ _
'
'
'
'
'
A
O------:-
- - - : - - - - - - - -
--
--
--,-
,
-,
'
'
'
'
Mt0/1 -
-+.
,
r:.---: .-.------------:
.~.L-
_.,
:.....
-+'
I+.
tO
~·
,.,...
1$
I
1
'
I
I
I
IAll
'
,----=~~~~---..;
.~
OME0/1
---T---~
'
'
'
'
'
'
.
'
'
'
'
'
··---+-' .
---- 7
'
- i
'
-
-c==========:
·
:
t·=)-
.
'
I
1
I
I
'
•+-
!
P
-:..:-- - -
--«- - - - - -
'
'
'
'
<
--,,--->:<
- -
--
-
- - - - -
-.;.>
"
'
'
'
tr'
and
'"'
for
actual
RO
M
is
as
f-ollows:
t
p·
=
t
,\
P
+
l
P
+
l
D
rn·
=
IA
-
ID
-
IS
1
s
=
200nS
S
ince
l..<\
P
and
to
differ
depending o
n
the
pcri1 >hcral
circuit
configuration.1heys
hould
be
cornputcd
on
1hc
basis
of
lo.ad
c.apacitancc.
3-4-3. Serial data input
SDI
is
a
serial data
transfer
input
and CLJ
serial data transfer
clock.
n ic
1
/
0
port
controller reads
the
input d<lla al the
rising
edge of
CU
.
Serial data goes
into the r'
C
cciving
111ode
\vhen
it
changes
fr()lll
an
idle
state
(SD
l=
I)
to
low·
state
a
nd
reads
data from
a
next
clock
.
SOI
=:x:
__
__,X~
_
__,
X~-
Cll
When
the 8-bit
darn
is
received
.
it
sets
the
receive
and
Oag
RD
active.
lf the
mask
l>it
is
on
at
this point.
interrupt
rcqucsl is
issued
to
the C
P
U.
RD
will
be
reset
upon read ing
the
8-bit
data
.
RD will
be
reset
in
a
course
of
serial
da
1
a
receiving.
which
is the
period
that
the
8-bit darn
is
being
rt:ccivcd.
\vith
(lu
t
includi
ng
the
s
iart
bit.
Do not sale this PDF!!!
Advertisement
