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PC-1500
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2-3-2. Interrupts
·nicrc
are following
three
k ind~
of interrupt
for
the
LH5801
CPU.
0
Non-maskable
interrupt
When
i\
MI
is
turned from
low
to
high level.
it
sets the
flipflop
I RO active.
u
pon
which
time
imcrrupt
is
requested
to
the
CPU. so
that the CP
U
starts
executing
the
interrupt
processing after con1plction
of
current
ins1ructi(>fl
execution.
Since
the
non-rnaskahlc
int.:rrt1pt
is
given
\Vith
the
highest
priority
t>rdcr.
c11e
interrupt
will
be
acknowledged
at
once.
regardless
of
its
internal
state.
IRO
'viii
be
reset
in
a
c(n1rst·
of
the
interrupt
process.
As
the
NIM
input
is
sampled by
the
clock
<PH.
it will
become
250k
Hnvhen
thc
4M H7
cfy~tal
osci llator
i~
connected.
<PH
CPU
intern.al
XL
O
d
Osclll
a
to1
XLI
S•;nch1oniLi11g-
-
-'
pu:Sc
mo
- -
--
--"
IT)SllUCIJOn
execute
ln
t<,:rJ
u
pt
t'c
knriwlo:."ft;~r:
<P
H
lntertvpl processing
/ ' Reset
IRO
\Vhcn
j\1
1\.
·
1 1
is
turned
high.
the
(:
F
'U creates synchronizing
pulse
at
the
rising edge
of
the
clock <l>H
,
which
sets
IRO
active.
If
IRO
is
active when
the
CPU
acknowl.:dged
the
inccrrupt
after
co111plcti<n1 <>f
execution.
it
g t)C'-S
into
the
interrupt
routine
an<l
I
RO
is
reset in
a
cour::;c
<>f t he
interrupt
processing.
17
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not
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