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12
All
and more
about
Sharp
PC-1
500
at
http://www.PC-1500.info
@
BRO
Bus
r<:q
ucst :;ignal.
@
BAK
flus
request
ackowlcdgc
signal.
When
BRQ
goes
high.
the CP
U issues
a high level of
sign.al
on
BAK in
response
to
it.
The
CPU
keeps address
bus
(ADO-
ADl5). data
bus
(00.-07).
MEO.
ME
I.
R/
W.
and
OD
high
impeda nce when
BAK
is
in high
level.
@
OPF
Operation C
«><.le
fetch signal \\lhich
is
sent
out \vhen CP
lJ
fetches operation C
<><ic
(insll'uction
code).
0
l'F
is
issue
d
on
ly
when opera1
ion
code
is
fowhcd n nd
will
not
be issued
in
fcwhi
ng
address
data.
in1media1e
data.
and
second
by1e
of
the
\\VO-step
instruction.
4>0
$
A~Aots
_
_ _ _ _
~X~--------~L
M
EO
OPF
@
INO-IN7
-,---------.
I
I
~-~-~
-
Lasi
I
Cyeie
_
,,_
_ _
Operation
cooe
_
_
__,
toteh
Inp
ut
port
through \Vhich the
C
l)\J
n:c-:ivts 8-hi1
data int<)
the
accun1u
lator
.
.
;\s
internal
pull
up resistor
is
used
.
the
CPU
assumes
it
to
be
high level when n.ol
connected.
@
p<P
External
latch
clock.
With
high level
of
this
clock
.
the contents
of
lite
<1ccumulator
is
sent on
the
data
bus.
Addi tion
of
IC will
comprise
an outpu
l
port.
REFE RENCE:
ATP instruction.
@PU,
PV
Thc:sc
arc
CPU
internal nipflo1
>
outputs.
PU
and
PV arc
furnished
wilh
sel and
reset
ins1ruci
ions.
Do not
sale
this PDF!!!
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