Memory Hole - Acorp 7KTA2 User Manual

Bhapter 1 Bhapter 1
Bhapter 1 Bhapter 1 Bhapter 1
DRAM Timary By SPD
The Choices: Enabled(default), Disabled.
DRAM Clock
This item determines DRAM Clock following the CPU
host clock.
The Choices: 100(default), 133.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of
clock cycle of CAS latency depends on the DRAM timing.
Do not reset this field from the default value specified by
the system designer.
The Choices: 3(default), 2, Auto.

Memory Hole

In order to improve performace, certain space in memory
can be reserved for ISA cards. This memory must be
mapped into the memory's space below 16MB.
The Choices: Diasbled(default), Enabled.
PCI Master Pipeline Req
The Choices: Enabled(default), Disabled.
P2C/C2P Concurrency
The item allows you to enable/disable the PCI to CPU to
PCI concurrency.
The Choices: Enabled(default), Disabled.
Fast R-W Turn Around
The item controls the DRAM timing.It allows you to
enable/disable the fast read/write turn around.
The Choices: Disabled(default), Enabled.
System BIOS Cacheable
When enabled, the access to the system BIOS ROM
address at F0000H-FFFFFFH is cached.
The Choices: Disabled(default), Enabled.
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BIOS Settp BIOS Settp
BIOS Settp BIOS Settp BIOS Settp