Processor 3/6 - Clevo N850HK1 Service Manual

Processor 3/6

5
NEAR CPU
1.0V_VCCST
R42
100_04 56.2_1%_04
D
49 H_CPU_SVIDDAT
49 H_CPU_SVIDALRT#
49 H_CPU_SVIDCLK
220_04
49,52 H_PROCHOT#
47 DDR_VTT_PG_CTRL
VCCST_PWRGD
R462 20_1%_04
26 H_PM_DOWN
R464 *12.1_1%_04
26 PCH_PECI
TO PCH-H
R465 *0402_short
42 H_PECI
TO EC
26 PCH_THERMTRIP#
C
VCCST_PWRGD
B
R430 20K_04
22,25,42,49 ALL_SYS_PWRGD
C571
*0.1u_10V_X7R_04
G
42 H_PROCHOT_EC
A
R510
100K_04
5
4 3
?
SKYLAKE _HA LO
U29E
BGA1440
R40 B31
29 PCH_CPU_BCLK_R_DP
BCLKP
A32
29 PCH_CPU_BCLK_R_DN BCLKN
D35
29 PCH_CPU_PCIBCLK_R_DP
PCI_BCLKP
C36
29 PCH_CPU_PCIBCLK_R_DN
PCI_BCLKN
E31
29 CPU_24MHZ_R_DP
CLK24P
D31
29 CPU_24MHZ_R_DN
CLK24N
R41
BH31
VIDALERT#
VIDALERT#
BH32
VIDSCK
BH29
H_PROCHOT# VIDSOUT
R460 499_1%_04 PROCHOT# BR30
PROCHOT#
BT13
DDR_VTT_CNTL
VCCST_PWRGD_CPU
R62 60.4_1%_04 H13
VCCST_PWRGD
BT31
27 H_PWRGD
PROCPWRGD
BP35
26 PLTRST_CPU_N
RESET#
BM34
26 H_PM_SYNC PM_DOWN PM_SYNC
BP31
PM_DOWN
BT34
PECI
PECI
J31
THERMTRIP#
H_SKTOCC_N
BR33
28 H_SKTOCC_N
SKTOCC#
BN1
PROC_SELECT#
BM30
CATERR#
5 OF 14
QHPW
REV = 1
1.0V_VCCST
VDD3
R61
1K_04
VCCST_PWRGD
R429
100K_04
D
SYS_PWRGD#
2 G C570
S Q36A
*0.1u_10V_X7R_04
D MTDK3S6R
5 G
S Q36B
MTDK3S6R
1.0DX_VCCSTG
H_PROCHOT#
R60 1K_04
Q41
C635
2SK3018S3 47P_50V_NPO_04
CAD Note: Capacitor need to be placed
close to buffer output pin
4 3
2
CFG[0]: Stall
PLL lock until de-asserted:
— 1 = (Default) Normal Operation;
No stall.
— 0 = Stall.
BN25 CFG0
T18
CFG[1]: Reserved
CFG[0]
BN27
CFG[1]
CFG[2]: PCI Express*
BN26
CFG[2]
BN28 Numbering Reversal.
CFG3
T96
CFG[3]
BR20 CFG4 R508 1K_04 — 1 = Normal operation
CFG[4]
BM20 CFG5 R91 1K_04 — 0 = Lane numbers reversed.
CFG[5]
BT20 CFG6 R509 1K_04 CFG[3]: Reserved
CFG[6]
BP20
CFG7 CFG[4]: eDP
T98
CFG[7]
BR23 CFG8
T99 — 1 = Disabled.
CFG[8]
BR22
— 0 = Enabled.
CFG[9]
BT23
CFG[6:5]:
CFG[10]
BT22
CFG[11] — 00 = 1 x8, 2 x4 PCI Express*
BM19
CFG[12] — 01 = reserved
BR19
CFG[13]
— 10 = 2 x8 PCI Express*
BP19
CFG[14]
BT19 — 11 = 1 x16 PCI Express*
CFG[15]
CFG[7]: PEG
BN23 — 1 = (default) PEG Train
CFG[17]
BP23 immediately following RESET# de
CFG[16]
BP22
assertion.
CFG[19]
BN22
— 0 = PEG Wait for BIOS for
CFG[18]
training.
BR27
BPM#[0] CFG[19:8]:
BT27
BPM#[1] lanes.
BM31
BPM#[2]
BT30
BPM#[3]
H_TDO
BT28
H_TDI
PROC_TDO
BL32
PROC_TDI H_TMS H_TDO
BP28
PROC_TMS H_TCK
BR28
PROC_TCK H_TCK
H_TRST#
BP30
PROC_TRST# H_PREQ#
BL30
PROC_PREQ# H_PRDY#
BP27
PROC_PRDY#
CFG_RCOMP
BT25
CFG_RCOMP
H_SKTOCC_N
R484
49.9_1%_04
?
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
CFG4
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
PCIE PORT BIFURCATION STRAPS
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
DEFENSIVE PULL DOWN SITE
CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
Title Title Title
[04]Processor 4/7-CLK/JTAG/MISC [04]Processor 4/7-CLK/JTAG/MISC [04]Processor 4/7-CLK/JTAG/MISC
3.3VA 9,24,25,26,27,30,32,50
1.0DX_VCCSTG 6,50,52
1.0V_VCCST 6,26,27,45,49
Size Size Size Document Document Document Number Number Number
6-71-N85H0-D01 6-71-N85H0-D01 6-71-N85H0-D01
VDD3 24,25,27,30,32,34,38,39,42,44,45,46,50,51,52,53,54,55,56
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
VCCIO 2,6,45,50
Date : Date : Date : Tuesday, October 11, 2016 Tuesday, October 11, 2016 Tuesday, October 11, 2016
2
Schematic Diagrams
1
reset sequence after PCU
configuration lane.
Static x16 Lane
D
configuration lane.
enable:
PCI Express* Bifurcation
Training:
Reserved configuration
1.0V_VCCST
R463 51_04
R483 51_04
C
Sheet 4 of 72
3.3VA
Processor 3/6
R486 100K_04
B
A
R e v R e v R e v
D01 D01 D01
Sheet Sheet Sheet 4 4 4 o f o f o f 63 63 63
1
Processor 3/6 B - 5