Processor 2/6 - Clevo N850HK1 Service Manual

Schematic Diagrams

Processor 2/6

8 M_A_DQ[63:0]
D
Sheet 3 of 72
Processor 2/6
C
B
A
B - 4 Processor 2/6
5 4
?
U29A SKYLAKE _HA LO
BGA1440
M_A_DQ0
BR6 AG1
M_A_DQ1 DDR0_DQ[0] DDR0_CKP[0]
BT6 AG2
M_A_DQ2 DDR0_DQ[1] DDR0_CKN[0]
BP3 AK1
M_A_DQ3 DDR0_DQ[2] DDR0_CKN[1]
BR3 AK2
M_A_DQ4
DDR0_DQ[3] DDR0_CKP[1]
BN5 AL3
M_A_DQ5 DDR0_DQ[4] DDR0_CLKP[2]
BP6 AK3
M_A_DQ6 DDR0_DQ[5] DDR0_CLKN[2]
BP2 AL2
M_A_DQ7 DDR0_DQ[6] DDR0_CLKP[3]
BN3 AL1
M_A_DQ8
DDR0_DQ[7] DDR0_CLKN[3]
BL4
M_A_DQ9 DDR0_DQ[8]
BL5 AT1
M_A_DQ10 DDR0_DQ[9] DDR0_CKE[0]
BL2 AT2
M_A_DQ11 DDR0_DQ[10] DDR0_CKE[1]
BM1 AT3
M_A_DQ12 DDR0_DQ[11] DDR0_CKE[2]
BK4 AT5
M_A_DQ13
DDR0_DQ[12] DDR0_CKE[3]
BK5
M_A_DQ14 DDR0_DQ[13]
BK1 AD5
M_A_DQ15 DDR0_DQ[14] DDR0_CS#[0]
BK2 AE2
M_A_DQ16 DDR0_DQ[15] DDR0_CS#[1]
BG4 AD2
M_A_DQ17
DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2]
BG5 AE5
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3]
BF4
M_A_DQ19 DDR0_DQ[18]/DDR0_DQ[34]
BF5 AD3
M_A_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0]
BG2 AE4
M_A_DQ21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[1]
BG1 AE1
M_A_DQ22
DDR0_DQ[21]/DDR0_DQ[37] DDR0_ODT[2]
BF1 AD4
M_A_DQ23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3]
BF2
M_A_DQ24 DDR0_DQ[23]/DDR0_DQ[39]
BD2 AH5
M_A_DQ25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
BD1 AH1
M_A_DQ26
DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
BC4 AU1
M_A_DQ27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
BC5
M_A_DQ28 DDR0_DQ[27]/DDR0_DQ[43]
BD5 AH4
M_A_DQ29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
BD4 AG4
M_A_DQ30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
BC1 AD1
M_A_DQ31
DDR0_DQ[30]/DDR0_DQ[46] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
BC2
M_A_DQ32 DDR0_DQ[31]/DDR0_DQ[47]
AB1 AH3
M_A_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
AB2 AP4
M_A_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
AA4 AN4
M_A_DQ35
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
AA5 AP5
M_A_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3]
AB5 AP2
M_A_DQ37 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4]
AB4 AP1
M_A_DQ38 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
AA2 AP3
M_A_DQ39 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
AA1 AN1
M_A_DQ40
DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
V5 AN3
M_A_DQ41 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
V2 AT4
M_A_DQ42 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
U1 AH2
M_A_DQ43 DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
U2 AN2
M_A_DQ44
DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
V1 AU4
M_A_DQ45 DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
V4 AE3
M_A_DQ46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
U5 AU2
M_A_DQ47 DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
U4 AU3
M_A_DQ48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
R2
M_A_DQ49
DDR0_DQ[48]/DDR1_DQ[32]
P5 AG3
M_A_DQ50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR
R4 AU5
M_A_DQ51 DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT#
P4
M_A_DQ52 DDR0_DQ[51]/DDR1_DQ[35]
R5
M_A_DQ53
DDR0_DQ[52]/DDR1_DQ[36]
P2 BR5
M_A_DQ54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0]
R1 BL3
M_A_DQ55 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1]
P1 BG3
M_A_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4]
M4 BD3
M_A_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5]
M1 AB3
M_A_DQ58
DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0]
L4 V3
M_A_DQ59 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1]
L2 R3
M_A_DQ60 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4]
M5 M3
M_A_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5]
M2
M_A_DQ62
DDR0_DQ[61]/DDR1_DQ[45]
L5 BP5
M_A_DQ63 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0]
L1 BK3
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1]
BF3
DDR0_DQSP[2]/DDR0_DQSP[4]
BA2 BC3
DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5]
BA1 AA3
DDR0_ECC[1] DDR0_DQSN[4]/DDR1_DQSN[0]
AY4 U3
DDR0_ECC[2] DDR0_DQSN[5]/DDR1_DQSN[1]
AY5 P3
DDR0_ECC[3] DDR0_DQSN[6]/DDR1_DQSN[4]
BA5 L3
DDR0_ECC[4] DDR0_DQSN[7]/DDR1_DQSN[5]
BA4
DDR0_ECC[5]
AY1 AY3
DDR0_ECC[6] DDR0_DQSP[8]
AY2 BA3
DDR0_ECC[7] DDR0_DQSN[8]
DDR CHANNEL A
1 OF 14
REV = 1
QHPW
?
5 4
3
U29B
9 M_B_DQ[63:0]
M_B_DQ0
BT11
M_A_CLK_DDR0 8 M_B_DQ1 DDR1_DQ[0]/DDR0_DQ[16]
BR11
M_A_CLK_DDR#0 8 M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[17]
BT8
M_A_CLK_DDR#1 8 M_B_DQ3 DDR1_DQ[2]/DDR0_DQ[18]
BR8
M_A_CLK_DDR1 8 M_B_DQ4
DDR1_DQ[3]/DDR0_DQ[19]
BP11
M_B_DQ5 DDR1_DQ[4]/DDR0_DQ[20]
BN11
M_B_DQ6 DDR1_DQ[5]/DDR0_DQ[21]
BP8
M_B_DQ7 DDR1_DQ[6]/DDR0_DQ[22]
BN8
M_B_DQ8
DDR1_DQ[7]/DDR0_DQ[23]
BL12
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24]
BL11
M_A_CKE0 8 M_B_DQ10 DDR1_DQ[9]/DDR0_DQ[25]
BL8
M_A_CKE1 8 M_B_DQ11 DDR1_DQ[10]/DDR0_DQ[26]
BJ8
M_B_DQ12 DDR1_DQ[11]/DDR0_DQ[27]
BJ11
M_B_DQ13
DDR1_DQ[12]/DDR0_DQ[28]
BJ10
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29]
BL7
M_A_CS#0 8 M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30]
BJ7
M_A_CS#1 8 M_B_DQ16 DDR1_DQ[15]/DDR0_DQ[31]
BG11
M_B_DQ17
DDR1_DQ[16]/DDR0_DQ[48]
BG10
M_B_DQ18 DDR1_DQ[17]/DDR0_DQ[49]
BG8
M_B_DQ19 DDR1_DQ[18]/DDR0_DQ[50]
BF8
M_A_ODT0 8 M_B_DQ20 DDR1_DQ[19]/DDR0_DQ[51]
BF11
M_A_ODT1 8 M_B_DQ21 DDR1_DQ[20]/DDR0_DQ[52]
BF10
M_B_DQ22
DDR1_DQ[21]/DDR0_DQ[53]
BG7
M_B_DQ23 DDR1_DQ[22]/DDR0_DQ[54]
BF7
M_B_DQ24 DDR1_DQ[23]/DDR0_DQ[55]
BB11
M_A_BA0 8 M_B_DQ25 DDR1_DQ[24]/DDR0_DQ[56]
BC11
M_A_BA1 8 M_B_DQ26
DDR1_DQ[25]/DDR0_DQ[57]
BB8
M_A_BG0 8 M_B_DQ27 DDR1_DQ[26]/DDR0_DQ[58]
BC8
M_B_DQ28 DDR1_DQ[27]/DDR0_DQ[59]
BC10
M_A_RAS# 8 M_B_DQ29 DDR1_DQ[28]/DDR0_DQ[60]
BB10
M_A_WE# 8 M_B_DQ30 DDR1_DQ[29]/DDR0_DQ[61]
BC7
M_A_CAS# 8 M_B_DQ31
DDR1_DQ[30]/DDR0_DQ[62]
BB7
M_B_DQ32 DDR1_DQ[31]/DDR0_DQ[63]
AA11
M_A_A0 8 M_B_DQ33 DDR1_DQ[32]/DDR1_DQ[16]
AA10
M_A_A1 8 M_B_DQ34 DDR1_DQ[33]/DDR1_DQ[17]
AC11
M_A_A2 8 M_B_DQ35
DDR1_DQ[34]/DDR1_DQ[18]
AC10
M_A_A3 8 M_B_DQ36 DDR1_DQ[35]/DDR1_DQ[19]
AA7
M_A_A4 8 M_B_DQ37 DDR1_DQ[36]/DDR1_DQ[20]
AA8
M_A_A5 8 M_B_DQ38 DDR1_DQ[37]/DDR1_DQ[21]
AC8
M_A_A6 8 M_B_DQ39 DDR1_DQ[38]/DDR1_DQ[22]
AC7
M_A_A7 8 M_B_DQ40
DDR1_DQ[39]/DDR1_DQ[23]
W8
M_A_A8 8 M_B_DQ41 DDR1_DQ[40]/DDR1_DQ[24]
W7
M_A_A9 8 M_B_DQ42 DDR1_DQ[41]/DDR1_DQ[25]
V10
M_A_A10 8 M_B_DQ43 DDR1_DQ[42]/DDR1_DQ[26]
V11
M_A_A11 8 M_B_DQ44
DDR1_DQ[43]/DDR1_DQ[27]
W11
M_A_A12 8 M_B_DQ45 DDR1_DQ[44]/DDR1_DQ[28]
W10
M_A_A13 8 M_B_DQ46 DDR1_DQ[45]/DDR1_DQ[29]
V7
M_A_BG1 8 M_B_DQ47 DDR1_DQ[46]/DDR1_DQ[30]
V8
M_A_ACT# 8 M_B_DQ48 DDR1_DQ[47]/DDR1_DQ[31]
R11
M_B_DQ49
DDR1_DQ[48]
P11
DDR0_A_PARITY 8 M_B_DQ50 DDR1_DQ[49]
P7
DDR0_A_ALERT# 8 M_B_DQ51 DDR1_DQ[50]
R8
M_B_DQ52 DDR1_DQ[51]
R10
M_A_DQS#0 M_A_DQS#[3:0] 8 M_B_DQ53
DDR1_DQ[52]
P10
M_A_DQS#1 M_B_DQ54 DDR1_DQ[53]
R7
M_A_DQS#2 M_B_DQ55 DDR1_DQ[54]
P8
M_A_DQS#3 M_B_DQ56 DDR1_DQ[55]
L11
M_A_DQS4 M_A_DQS[7:4] 8 M_B_DQ57 DDR1_DQ[56]
M11
M_A_DQS5 M_B_DQ58
DDR1_DQ[57]
L7
M_A_DQS6 M_B_DQ59 DDR1_DQ[58]
M8
M_A_DQS7 M_B_DQ60 DDR1_DQ[59]
L10
M_B_DQ61 DDR1_DQ[60]
M10
M_A_DQS0 M_A_DQS[3:0] 8 M_B_DQ62
DDR1_DQ[61]
M7
M_A_DQS1 M_B_DQ63 DDR1_DQ[62]
L8
M_A_DQS2 DDR1_DQ[63]
M_A_DQS3
AW11
M_A_DQS#4 M_A_DQS#[7:4] 8 DDR1_ECC[0]
AY11
M_A_DQS#5
DDR1_ECC[1]
AY8
M_A_DQS#6 DDR1_ECC[2]
AW8
M_A_DQS#7 DDR1_ECC[3]
AY10
DDR1_ECC[4]
AW10
DDR1_ECC[5]
AY7
DDR1_ECC[6]
AW7
DDR1_ECC[7]
DDR CHANNEL B
CLOSE TO CPU
DDR_RCOMP0
G1
R560 121_1%_04
DDR_RCOMP1 DDR_RCOMP[0]
R562 75_1%_04 H1
DDR_RCOMP2
DDR_RCOMP[1]
R563 100_1%_04 J2
DDR_RCOMP[2]
QHPW
3
2 1
?
SKYLAKE _HA LO
BGA1440
AM9
DDR1_CKP[0] M_B_CLK_DDR0 9
AN9
DDR1_CKN[0] M_B_CLK_DDR#0 9
AM8
DDR1_CKN[1] M_B_CLK_DDR#1 9
AM7
M_B_CLK_DDR1 9
DDR1_CKP[1]
AM11
DDR1_CLKP[2]
AM10
DDR1_CLKN[2]
AJ10
DDR1_CLKP[3]
AJ11
DDR1_CLKN[3]
AT8
DDR1_CKE[0] M_B_CKE0 9
AT10
DDR1_CKE[1] M_B_CKE1 9
AT7
DDR1_CKE[2]
AT11
DDR1_CKE[3]
AF11
DDR1_CS#[0] M_B_CS#0 9
AE7
DDR1_CS#[1] M_B_CS#1 9
AF10
DDR1_CS#[2]
AE10
DDR1_CS#[3]
AF7
DDR1_ODT[0] M_B_ODT0 9
AE8
DDR1_ODT[1] M_B_ODT1 9
AE9
DDR1_ODT[2]
AE11
DDR1_ODT[3]
AH10
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M_B_RAS# 9
AH11
M_B_WE# 9
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AF8
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M_B_CAS# 9
AH8
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_BA0 9
AH9
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_BA1 9
AR9
M_B_BG0 9
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AJ9
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] M_B_A0 9
AK6
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A1 9
AK5
M_B_A2 9
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
AL5
DDR1_MA[3] M_B_A3 9
AL6
DDR1_MA[4] M_B_A4 9
AM6
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A5 9
AN7
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A6 9
AN10
M_B_A7 9
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
AN8
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A8 9
AR11
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A9 9
AH7
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A10 9
AN11
M_B_A11 9
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
AR10
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] M_B_A12 9
AF9
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M_B_A13 9
AR7
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M_B_BG1 9
AT9
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# M_B_ACT# 9
AJ7
DDR1_PAR DDR1_B_PARITY 9
AR8
DDR1_ALERT# DDR1_B_ALERT# 9
M_B_DQS#0 M_B_DQS#[3:0] 9
BP9
DDR1_DQSN[0]/DDR0_DQSN[2] M_B_DQS#1
BL9
DDR1_DQSN[1]/DDR0_DQSN[3] M_B_DQS#2
BG9
DDR1_DQSN[2]/DDR0_DQSN[6] M_B_DQS#3
BC9
DDR1_DQSN[3]/DDR0_DQSN[7] M_B_DQS#4 M_B_DQS#[7:4] 9
AC9
M_B_DQS#5
DDR1_DQSN[4]/DDR1_DQSN[2]
W9
DDR1_DQSN[5]/DDR1_DQSN[3] M_B_DQS#6
R9
DDR1_DQSN[6] M_B_DQS#7
M9
DDR1_DQSN[7]
M_B_DQS0 M_B_DQS[3:0] 9
BR9
DDR1_DQSP[0]/DDR0_DQSP[2] M_B_DQS1
BJ9
DDR1_DQSP[1]/DDR0_DQSP[3] M_B_DQS2
BF9
DDR1_DQSP[2]/DDR0_DQSP[6] M_B_DQS3
BB9
DDR1_DQSP[3]/DDR0_DQSP[7] M_B_DQS4 M_B_DQS[7:4] 9
AA9
M_B_DQS5
DDR1_DQSP[4]/DDR1_DQSP[2]
V9
DDR1_DQSP[5]/DDR1_DQSP[3] M_B_DQS6
P9
DDR1_DQSP[6] M_B_DQS7
L9
DDR1_DQSP[7]
AW9
DDR1_DQSP[8]
AY9
DDR1_DQSN[8]
BN13
DIMM_CA_CPU_VREF_A 8
DDR_VREF_CA DIMM_DQ_CPU_VREF_A
BP13
DDR0_VREF_DQ
BR13
2 OF 14 DDR1_VREF_DQ DIMM_DQ_CPU_VREF_B 9
REV = 1
?
Title Title Title
[03] Processor 3/7-DDR4 [03] Processor 3/7-DDR4 [03] Processor 3/7-DDR4
Size Size Size Document Document Document Number Number Number R e v R e v R e v
6-71-N85H0-D01 6-71-N85H0-D01 6-71-N85H0-D01
D01 D01 D01
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date : Date : Date : Tuesday, October 11, 2016 Tuesday, October 11, 2016 Tuesday, October 11, 2016 Sheet Sheet Sheet 3 3 3 o f o f o f 63 63 63
2 1
D
C
B
A