Pch 9/9 - Clevo N850HK1 Service Manual

PCH 9/9

5
NO REBOOT STARP
ENABLE: HIGH
(INTERNAL WEAK PD)
3.3VS
R209
D *4.7K_04
LPSS_GSPI0_MOSI
BOOT STARP
ENABLE:LPC IS SELECT
(INTERNAL WEAK PD)
3.3VA
R199
*4.7K_04
LPSS_GSPI1_MOSI
C
R581
28,32,35 ASM_SMI#
R582
28,32,35 ASM_SMI#
DEBUG
TX -> D+
RX -> D-
B
A
5
4 3
SP T-H_P CH
U45J
BD2 AR22 RSVD22
VSS RSVD
BD45 W13
VSS RSVD
BD44 U13
VSS RSVD
BE44 P31
VSS RSVD
D45 N31
VSS RSVD
A42
VSS
B45 P27
VSS RSVD
B44 R27
VSS RSVD
A4 N29
VSS RSVD
A3 P29
VSS RSVD
B2 AN29
VSS RSVD
A2 R24
VSS RSVD
B1 P24
VSS RSVD
BB1
VSS PCH_XDP_PREQ#_R
BC1 AT3
VSS PREQ# PCH_XDP_PRDY#_R
A44 AT4
H_TRST#_R
VSS PRDY#
AY5
CPU_TRST# PCH_2_CPU_TRIGGER_R
C1 AL2
RSVD PCH_TRIGOUT
D1 AK1
RSVD PCH_TRIGIN
HM170 10 OF 12 REV = 1.3
SP T-H_P CH
U45K
LPSS_GSPI1_MOSI
AT29
GPP_B22/GSPI1_MOSI
AR29
GPP_B21/GSPI1_MISO
AV29
GPP_B20/GSPI1_CLK
BC27
GPP_B19/GSPI1_CS#
LPSS_GSPI0_MOSI
BD28
GPP_B18/GSPI0_MOSI
BD27
GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#
AW27
GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#
AR24
GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
AV44
GPP_C9/UART0_TXD
BA41
GPP_C8/UART0_RXD
AU44
GPP_C11/UART0_CTS#
AV43
GPP_C10/UART0_RTS#
AU41
GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL
AT44
Open Cover
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AT43
GPP_C13/UART1_TXD/ISH_UART1_TXD
AU43
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
0_04 USB3.1 AN43
GPP_C23/UART2_CTS#
*0_04 AN44
UART2_TXD GPP_C22/UART2_RTS#
AR39
UART2_RXD GPP_C21/UART2_TXD
AR45
GPP_C20/UART2_RXD GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
AR41
GPP_C19/I2C1_SCL GPP_A21/ISH_GP3
AR44
GPP_C18/I2C1_SDA GPP_A20/ISH_GP2
AR38
GPP_C17/I2C0_SCL GPP_A19/ISH_GP1
AT42
GPP_C16/I2C0_SDA GPP_A18/ISH_GP0
GPP_A17/ISH_GP7
AM44
GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
AJ44
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL
HM170 11 OF 12 REV = 1.3
4,24,25,27,30,34,38,39,42,44,45,46,50,51,52,53,54,55,56
8,9,17,18,20,21,22,23,24,26,27,28,29,30,34,35,38,39,40,41,42,43,44,49,53,54,55,56
4 3
2
DFX TEST MODE QUALIFIER FOR OTHER
DFX STRAP WHEN SAMPLED LOW
(WEAK INTERNAL PU)
R608 30.1_1%_04
PCH_2_CPU_TRIGGER 6
CPU_2_PCH_TRIGGER 6
GPIO
H: W / TPM
L: W/O TPM
BIOS
BOARD_ID1
AL44
R580 *10K_04
3.3VS
GPP_D9 BOARD_ID2
AL36
R583 *10K_04
GPP_D10
AL35
TPM_DET
GPP_D11
AJ39 R201 *10K_04
GPP_D12 3.3VS
R203 *10K_04
AJ43
AL43
AK44 BIOS check, D02
AK45
BC38
BB38
BD38
BE39
DGPU_PWM_SELECT#
BC22
T116
BD18
SATA_PWR_EN 39
BE21
3G_CONFIG2
BD22
T104
3G_CONFIG3
BD21
T105
SB_BLON
BB22
SB_BLON 22
BC19
BIOS
SB_BLON
4,9,24,25,26,27,30,50 3.3VA
VDD3
Title Title Title
[32] PCH 10_11/12-UART/I2C/GPIO [32] PCH 10_11/12-UART/I2C/GPIO [32] PCH 10_11/12-UART/I2C/GPIO
3.3VS
Size Size Size Document Document Document Number Number Number
6-71-N85H0-D01 6-71-N85H0-D01 6-71-N85H0-D01
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date : Date : Date : Tuesday, October 11, 2016 Tuesday, October 11, 2016 Tuesday, October 11, 2016
2
Schematic Diagrams
1
D
3.3VS
Sheet 32 of 72
R208
10K_04
BIOS TPM
PCH 9/9
TPM_DET
R205
*100K_04
C
W/O TPM
B
VDD3
R631 *10K_04
A
R e v R e v R e v
D01 D01 D01
Sheet Sheet Sheet 32 32 32 o f o f o f 63 63 63
1
PCH 9/9 B - 33