Vcc_Core & Vccgt - Clevo N850HK1 Service Manual

Schematic Diagrams
VCC_Core & VCCGT
D
Sheet 49 of 72
VREF_VCORE
VCC_Core &
C
VCCGT
B
A
B - 50 VCC_Core & VCCGT
8 7 6
Intel SKYLAKE IMVP8 POWER CKT - 2+1 PHASE
VREF_VCORE
CORE Max Switching
VIN
PR55 1_1%_06 PR54 560K_1%_06
PC25
VBOOT=0.8V
0.22u_50V_Y5V_06
VIN
FOR CV
5V
2 1 PR59 1_1%_06 PR50 499K_1%_06
PJ4 *CV-40mil
PJ3 1 2 1mm PC23
0.22u_50V_Y5V_06
GT Max Switching Frequency=425Khz
VCORE
PR268
100_04
Default SHORT
1 2 43.2K_1%_04
PJ6 1mm PR37 10K_1%_04
5 VCC_VCORE_SENSE
PC13 PC14 PC12
*1000p_50V_X7R_04 100p_50V_NPO_04
*1000p_50V_X7R_04
1 2
PJ5 1mm
5 VSS_VCORE_SENSE
PR39 PC2
100_04
*1000p_50V_X7R_04
VCCGT
PR291
100_04
Default SHORT
1 2
PJ7 1mm PR41
7 VCCGT_SENSE
PC16 PC18
*1000p_50V_X7R_04
*1000p_50V_X7R_04
PJ8 1 2 1mm
7 VSSGT_SENSE
PR31
PC10
100_04
*1000p_50V_X7R_04
8 7 6
5 4
VCORE IMON GT IMON
VREF_VCORE
PR12
PR221 0_04
0_04
PR220
33.2K_1%_04 PR11
56K_1%_04
10k ntc
RT3 RT1
100k_1%_04_NTC EWTF02-103F3I-N
PR8 0_04 1.0V_VCCST
VREF_VCORE
PR90
*1K_1%_04
PR10
1_04
H_PROCHOT#
PR2
PC1 PR3
PR4
Frequency=421Khz
D02
PR52 0_04 40
NC
TONSET 48
TONSET
TONSETA 38
TONSETA
RT3606BE
43
48 DRVON1 PS4
SET1 12
SET1
SET2 13
GND
SET2
SET3 14
SET3
15
SETA1
SETA1
SETA2 16
SETA2
10
VSEN
PR34
9 PU1 RT3606BEGQW
COMP
8
FB
PC11
82p_50V_NPO_04
11
RGND
PR248 PC132
2.2_06
5V
VCORE_PG 25
PR218
*0_04
PR53
10K_1%_04 PR42 18K_1%_04
10K_06 OFSM
PR223
PC17 PC19 3.3VS 0_04
82p_50V_NPO_04 220p_50V_NPO_04
8,9,17,18,20,21,22,23,24,26,27,28,29,30,32,34,35,38,39,40,41,42,43,44,53,54,55,56
5 4
3 2
H-line 42
1.0V_VCCST
PC36
1u_6.3V_X5R_04 3.3VS
2 1 PR32 10K_04
*CV-40mil
PJ1
1 2
ALL_SYS_PWRGD 4,22,25,42
PJ2 OPEN_4mil
4,52
49.9_1%_04
H_CPU_SVIDCLK 4
10_04 PR1
H_CPU_SVIDDAT 4
0_04
0_04
H_CPU_SVIDALRT# 4
VR_ENABLE
PC24 0.1u_16V_X7R_04
C1
PR60 330K_1%_06 *0.1u_10V_X7R_04
VIN
PR51 100K_1%_04
D02
39
DVD
5V
PSYS&OFSA
45
PWM1 PWM11 48
44
PR219
PWM21 48
PWM2
*0_04
46
PWM3
PR250
unused floating. *0_04
PSYS 52
26 OFSA/PSYS
OFSA/PSYS
5
PR222
ISEN1P CSP11 48
20K_04
4
PR43 680_1%_04
CSN11 48
ISEN1N
GT
6
NO Load Offset
ISEN2P CSP21 48
PSYS DISABLE
7 PR44 680_1%_04
ISEN2N CSN21 48
2
ISEN3P
3 PR244 10K_06
5V
ISEN3N
The unused ISENAxP pins are recommended to be connected to VCC
42
PWM12 48
PWMA1
41
PWMA2
unused floating.
CSP12 48
PR46 680_1%_04
CSN12 48
PR249 10K_06
5V
5V
CORE
NO Load Offset DISABLE
4,6,26,27,45 1.0V_VCCST
22,27,44,45,46,47,48,51,52,53,54,55 VIN
36,37,39,44,47,48,50,51,55,56 5V Title Title Title
[49] VCC_CORE & VCCGT [49] VCC_CORE & VCCGT [49] VCC_CORE & VCCGT
6,51 VCCSA
3.3VS
5,48 VCORE
Size Size Size Document Document Document Number Number Number
6-71-N85H0-D01 6-71-N85H0-D01 6-71-N85H0-D01
7,48 VCCGT
Custom Custom Custom SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date : Date : Date : Thursday, November 03, 2016 Thursday, November 03, 2016 Thursday, November 03, 2016 Sheet Sheet Sheet
3 2
1
D
C
B
A
R e v R e v R e v
D01 D01 D01
49 49 49 o f o f o f 63 63 63
1