Sharp FO-CC500 Service Manual page 64

FO-CC500A
FO-K01A
1) Technical Overview
This section provides a technical description of the Merlin device set
and how it is used to implement all 900 MHz and 2.4 GHz cordless
telephone features. The device set is used both in the handset and
the base station as shown in Fig. 9.
Serial EEPROM
Second Codec
Codec
BS/HS interface
Keypad/LCD/
Switches/LEDs
Vbattery
Resetln
Park
RXI
RXQ
AGC
LNA
2) System Controller
The system controller handles all telephone features, the DSS en-
gine, the RF module settings, and the link between the base station
and the handset.
The system controller provides a microcontroller, interrupt controller,
wait-state generator, and system timer support. The system control-
ler also provides General Purpose I/O (GPIO) and serial ports for
peripheral control, a baseband modem (DSS engine) for signal
processing of the received and transmitted data, and a DSP core for
ADPCM conversion and CID support.
Microcontroller. The microcontroller is the 65C02-based MC19CPU.
It is supported by 2 kB of on-chip RAM and 48 kB of on-chip ROM.
The CPU communicates with the internal memory via a 16-bit ad-
dress/8-bit data bus and dedicated control lines.
The 128-pin Merlin XROM also has an address/data bus available for
accessing external memory.
MC19 Controller
& Address Decoder Logic
Serial Ports/Timers
GPIO Configurable
Port B
Codec Serial Port
ART/Timer B
Timer A
Keypad GPIO
Low Battery Detector
Watchdog/Sleep Timer
Reset
Park Detect
Baseband Modem
(Digital Spread - Spectrum Engine)
RX Data Path Time Division
demodulator dupiex controller
descrambler & clock
generator
DAC
AGC
Logic
Fig. 9 Merlin ASIC Block Diagram
DSP Core
ADPCM,tone generation,
CAS detection,SDT detection
CID demodulation,
HDX speakerphone support
ROM(48kB)
RAM(2kB)
RF GPIO
configurable Port C
Phone GPIO
configurable Port A
Controller Interface
DAC
OSC
TX Data Path
modulator
scrambler
spreader
Interrupt Controller. Interrupts are latched, prioritized, and passed
to the microcontroller. Interrupts are used to interface with the Codec,
the DSS engine, serial ports, and timers.
Wait-State Generator. Slower access times for off-chip RAM and ROM
are handled separately with programmable wait states. Off-chip reads/
writes can be extended up to seven clock cycles.
Watchdog/Sleep/Wake-Up Timers. These timers perform two basic
functions. They provide a reset if the software malfunctions (watch-
dog). They also minimize power consumption by keeping a low-fre-
quency clock active to duty-cycle the system between normal mode
and stand-by mode (sleep and wake-up timer).
Emulator/Test Interface. A standard 65C02-family parallel interface
supports an external emulator for code development.
ROM is mapped off-chip when operating with an emulator.
Emulator functions are only provided with the Merlin XROM ASIC.
5 – 14
RF Interface
Power control
Synthesizer control
Telephone Interface
Hook/Ringer/LEDs/
Other miscellaneous
Emulator/Test/
Parallel Interface
(128-pin ASIC only)
Data bus,Address bus
Bus control signals
19.2MHz
Inverter
TCXO
TXD