Pt580 F5 Schematic Diagram (Main Board_Cpu Clock) - Hytera PT580 Service Manual

Tetra portable terminal
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PT580 F5 Schematic Diagram (Main Board_CPU Clock)

D
1V6D
C2024
TO CLOCK
2
12MHz_CLK
C
C2001
B
C2005
1V6D
R2001
1V6D
R2002
1V6D
A
1
2
3
PT580 F5 MAIN BOARD SCH.(CPU_CLOCK)
12MHz_CPU
1V6D
4
R2008
12MHz_CPU
U2002
32K_CLK
3V3D
3V3D
FP_IO1
FP_IO2
FP_IO3
U2001A
1V6D
A15
CVDD
C2002
C2003
C2004
M2
CVDD
Y9
CVDD
Y20
Vcore
CVDD
AA3
CVDD1
A3
CVDD2
C2006
C2007
C2008
A9
CVDD2
E2
Vmpu
CVDD2
B13
CVDD3
B20
CVDD3
J21
Vdsp
CVDD3
R20
CVDD3
C2009
Y21
CVDDA
Vapll
A11
CVDDDLL
C2010
Vddr
W12
CVDDRTC
Vrtc
C2011
N1
Vss
P12
Vss
R21
Vss
U2
Vss
W20
Vss
GND
Y3
Vss
AA1
Vss
AA7
Vss
AA21
Vss
Y13
Vss
3
4
5
U2001B
Y2
OSC1_IN
W3
OSC1_OUT
CLOCK
RESET
V13
OSC32K_IN
AA13
OSC32K_OUT
P13
CLK32K_IN
R2011
Y12
RTC_ON_NOFF
R2012
J20
MPU_BOOT/USB1.SUSP
N19
GPIO13/KB.R[5]/LCD.BLUE0
R2013
V18
CONF
R10
MCLKREQ/EXT_MASTER_REQ/UART2.RX/MMC2.DAT3/GPIO23
V5
MCLK/MMC2.DATDIR0/GPIO24
IO
3V3D
V12
DVDDRTC
Vrtcio
A19
DVDD1
E21
C2012
C2013
C2014
C2015
DVDD1
AA2
DVDD2
Y7
DVDD3
AA11
DVDD6
Vio
Y16
C2016
C2017
C2018
C2019
DVDD7
L21
DVDD8
U21
DVDD9
1V8D
A5
DVDD4
A7
C2020
C2026
C2025
DVDD4
B10
DVDD4
Vsdram
B14
DVDD4
3V3D
C2
DVDD5
H2
C2021
C2022
DVDD5
R1
DVDD5
Vflashio
J1
LDO.FILTER
C2023
A13
Vss
A21
Vss
B1
Vss
B5
Vss
B7
Vss
B16
Vss
F20
Vss
G1
Vss
K2
Vss
K20
Vss
4
5
68
6
3V3D
R2016
U20
MPU_RST/MPUIO14
R12
PWRON_RESET
/RESET
AA20
RST_OUT/GPIO41
/RST_OUT
W17
EMU1
EMU1
V16
EMU0
EMU0
Y17
R2018
RTCK
RTCK
W18
TCK
TCK
JTAG
Y19
TDI
TDI
V17
TMS
TMS
Y18
TRST
/TRST
AA19
R2019
TDO
TDO
6
7
8
D
C
B
A
7
8

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