Mitsubishi QD51-R24 User Manual page 57

Melesec q series
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3 SPECIFICATIONS
3 - 22
(4) Buffer Memory Addresses
Addresses in buffer memory differ depending on whether they are designated by
the programmable controller CPU or by a BASIC program, and are as follows.
(a)
If designated from the programmable controller CPU
If designated by the programmable controller CPU, addresses are in 1-
word units.
Also, buffer memory addresses are designated from 0
hexadecimal notation.
(b)
If designated by a BASIC program
If designated by a BASIC program, addresses are in 1-byte units.
Also, buffer memory addresses are designated from 0
hexadecimal notation.
Designated from the
programmable
controller CPU using
a FROM/TO command.
(1-word units)
Buffer Memory
0
Lower order 8 bits
H
0
H
1
Higher order 8 bits
H
2
Lower order 8 bits
H
1
H
3
Higher order 8 bits
H
Lower order 8 bits
17FC
BFE
H
17FD
Higher order 8 bits
Lower order 8 bits
17FE
BFF
H
Higher order 8 bits
17FF
MELSEC-Q
to BFF
in
H
H
to 17FF
in
H
H
Address designated by
GETMEM / PUTMEM
in a BASIC program.
(1-byte units)
H
H
H
H
3 - 22

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