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3 SPECIFICATIONS
3.5.2 Buffer memory
3 - 20
Buffer memory is memory for carry out sending and receiving of data between the
QD51 (-R24) and the programmable controller CPU.
(Data from the programmable controller CPU that are written to buffer memory can be
read from multiple tasks. Data written to buffer memory from multiple tasks can be read
from the programmable controller CPU.)
(1) Reading/Writing of Data
(a)
Data from the programmable controller CPU are read from or written to the
buffer memory by the FROM/TO command.
Program example
The following shows a program where values in D0 to D9 are written
into the buffer memory area addressed 0
execution start signal (X0B) is ON.
To write data from the programmable controller CPU to the buffer
memory or to read data from the buffer memory, use the multitask
execution start signal (X0B) as an interlock.
Write
Command X0B
Sequence
Program
(1-word units)
Interlock that enables or disables FROM/TO execution.
0
H
1
H
TO
to
(Writing of data)
8
H
9
H
MELSEC-Q
to 9
when the multitask
H
H
T0 H0 H0 D0 K10
QD51(-R24)
Buffer Memory
0
H
1
H
2
H
3
H
to
10
H
11
H
12
H
13
H
3 - 20
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