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13.
7.
1
Slot Selector Circuit
The
slot
selector circuit divides
the
64K
byte
memory
area into four parts
of
16K
bytes each
according
to
the
values of
the
PPI
PA
ports
PAO
thru
PA7, and
allocates
each
part
to a correspond-
ing
slot
0 thru
3.
When
the
system
is
reset,
all
PPI ports
become
input
ports
at
high
impedance,
resulting
in
the
SLTE
signal
becoming
H
for
automatic
selection
of
slot
0
(to
activate
MSX-BASIC
as
indicated
in
Table
13-10*).
Once
the
PPI
is
accessed,
however,
SLTE
becomes
L
to enable
slots
to
be
selected
according to
PA
port
data.
Fig.
13-30
Slot
selector circuit
Table 13-10
"0"
in this
table
denotes
l_,
and "1" denotes
H
level.
•
Slot selection
Slots are selected
by
PA
ports
in
the following
way.
The
function of the
CSnH
and
CSnL
signals
(where n = 0
to
3) for
PAO
thru
PA7
is
to specify
addresses for
each
16K
bytes,
and
to specify
the
corresponding
slots
(0 thru
3)
for those addresses.
These
CSnH/L
signals
can be considered
as
CSn
and
SLT H/L
elements
in
the
following
way.
(1)
CSn
(where n
= 0
to 3) specified
addresses for
each
16K
bytes (page
0
thru
3)
(2)
SLTH
and
SLTL
specify
slots
0
thru
3
in
two-bit binary
That
is,
the
CSnH/L
signals
determine which
16K
bytes
in
the
slot
0 thru 3
X
64K
byte
memory
matrix
is
to
be used to
form
a
64K
byte
X
1
memory
which
can be handled
by
the
CPU.
For example,
to
form
a
64K
byte
memory
area
using the four
16K
byte
memory
areas indicated
by
the
shaded
sections
(a,
f,
k,
and
p)
in
Fig.
13-31,
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