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PX-7
WAVEFORM
®
2V/div
WAVEFORM
©
2V/div
13.
20
Synchronizing
Pulse
Generator
(Gate
Array
1C 102)
The
synchronizing
pulse generator
consists
of
the following
component
circuits.
(1)
External horizontal synchronizing
signal
noise
remover
(2)
External video
signal
detector
(3)
VDP
clock generator
(4)
VDP
clock generation
reference
signal
generator
(5)
Reference
signal
switching
circuit
for
the
horizontal
and
vertical
synchronizing
signals
plus
PLL
generator
used
in
picture synthesis
(6)
Burst gate pulse generator
(7)
PAL
pulse generator
(8)
Computer
sound muting
control
circuit
Operation of
the
synchronizing
pulse generator
differs
considerably
in
computer
mode
and
external
video/picture synthesis
mode.
• Computer
mode
When
in
computer
mode
(VOVLY
=
H), the gate
array
internal
connections
are as
shown
in
Fig.
13-57.
In
computer mode,
the
vertical
and com-
posite
synchronizing
signals
separated
from
the
computer
picture
output
signal
from
the
VDP
(TMS9129)
are applied to
the
IN
VS
and
INHS
pins
(pins
9 and
8).
The
output
from
pin
13
(VSYNC)
is
inverted
by
the
IC109(6/6)
driver
and
applied
as
a negative
vertical
synchronizing
signal
to the
RGB
terminal
(pin
5).
And
the
composite
synchronizing
signal
from
pin
14
(HSYNC)
is
NORed
with the
vertical
synchronizing
signal at
the
1C106
driver
to
remove
the
vertical
synchroniz-
ing
component
before being applied
as
a
negative
horizontal
synchronizing
signal
to the
RGB
ter-
minal
(pin
4).
The
color subcarrier
(4.433618MHz)
is
applied
to
pin
17 (CKI1) from
the
color subcarrier
oscilla-
tor,
and
divided
by 1136
in
the frequency
divider
to
obtain a
3.903kHz
signal
which
is
applied
as
a
reference
signal
to the phase comparator.
The
VCO
output (10.67815MHz),
on
the other hand,
is
applied to pin
29
(CKI2) where
it
is
rectified
by
a
Schumitt
buffer
and
passed as the
VDP
clock
from
pin
30 (CK02).
Part of
this
output
is
divided
once
by
684
and
again
by
4
(overall division
by
2736)
to
become
a
3.903kHz comparator
signal
to
be
applied
to
the
phase
comparator.
The
phase
comparator output
thus
forms
a
loop with the loop
filter
and
VCO
which
in
turn
forms a
PLL
oscillator
circuit
based
on
the divided
signal
obtained
from
the color
subcarrier.
A
horizontal synchronizing
signal
obtained
by
dividing
the
VDP
clock
(10.67815MHz) by 684
is
combined
with a
vertical
synchronizing
signal
separated
from
the external
video
signal
and
applied to pin
25
(RSYNC).
When
there
is
no
external
video
signal
applied
to
pin
28
(EXTV)
(that
is,
no
input applied to
pin 7
(EXSI)), the counter
and
FF2
are
not
reset
—
the
counter
is
incremented
by
the
output
from
a
frequency
halving
circuit,
and
FF2
remains
in
a
triggered state
with an
H
output
on
pin 28.
When
an
external
video
signal
is
then
applied,
a
composite
synchronizing
signal
(external
synchronizing
signal)
is
applied to pin 7 (EXSI),
and
the
counter and
FF2
are
reset
by
the
h
orizonta
l
synchronizing
signal in
the
input.
Pin
28 (EXTV)
is
thus
changed
to
L
level.
However,
since
the counter
divides the
7.806kHz
signal
(halved horizontal
synchronizing
signal)
by
7,
FF2
is
inverted
if
more
than 14
pulses (897/^S
MIN.)
have
been
extracted
from
the
horizontal
synchr
onizing
signal
from
pin 7 (EXSI),
and
the pin
28
(EXTV)
output
is
changed
to
H
level.
Hence,
the pin
28 output
serves as
a detector
signal
which
is
H
when
no
external
video
signal
is
applied
and
L when
a
signal
is
applied.
The
same
HSYNC
composite
synchronizing
signal
is
also
passed
from
pin
3
(EXHP1).
to pin 4
(FH)
via
the
horizontal
synchronizing
signal
processing
circuit.
This
FH
is
then applied to the
PAL
pulse generator together with the halved
and
inverted
CKI1, and
a
PAL
pulse
output
signal
which
controls
the
PAL
switch with a pulse
width
of
about 450ns and which
is
triggered
by
the
FH
trading
edge
is
obtained
from
pin
15
(PAL PULSE).
(Delay time: 0 to 450ns). Furthermore, the
HSYNC
(composite synchronizing
signal)
obtained
from
117
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